Method for fabricating power transistor using silicon-on-insulat

Details Method for fabricating power transistor using silicon-on-insulat Method for fabricating power transistor using silicon-on-insulat

1996-11-01

1998-12-29

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438430, H01L 21336, H01L 2126

Patent

active

058541136

ABSTRACT:
An improved method for fabricating a power transistor using an SOI wafer which is capable of using an SOI substrate having a thin Si film, which includes the steps of a first step for forming an SOI layer having a first oxidation film and a single crystal Si thin film by implanting an oxygen ion with respect to a single crystalline substrate and heat-treating the same, a second step for forming source and drain electrodes of a first poly-crystal Si film encircled by a third oxidation film on the SOI substrate, a third step for forming a shallow junction by ion-implanting with respect to the source and drain electrodes of the first poly-crystalline Si film, a fourth step for forming a second poly-crystalline Si film by a reactive ion etching method with respect to the third oxide film so as to form a gate electrode, and a fifth step for stabilizing a voltage at a lower channel portion, which voltage is supplied thereto through a p-type region of the SOI layer, and for ion-implanting a p-type dopant ion using a photoresistive film as a mask so as to supply a voltage to the lower portion of the SOI layer beneath the channel portion, and for forming source and drain electrode.

REFERENCES:
patent: 5389561 (1995-02-01), Gomi
patent: 5554546 (1996-09-01), Malhi

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