Method for fabricating power mosfet

Details Method for fabricating power mosfet Method for fabricating power mosfet

2007-04-03

2007-04-03

Pham, Thanhha (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S138000, C438S156000

Reexamination Certificate

active

10906166

ABSTRACT:
A method for fabricating a power MOSFET, comprising an epitaxial layer, a gate dielectric layer and a gate layer formed on a substrate, the gate dielectric layer and the gate layer defined to form a gate structure, a stacked mask and the surface of the epitaxial layer partially exposed between the gate structure and the stacked mask, a well region formed in the epitaxial layer and partially under the gate structure and the stacked mask, a source region is formed in the well region between the gate structure and the stacked mask, a patterned dielectric layer exposing the top of the stacked mask formed over the substrate, the stacked mask removed to form a contact opening exposing the surface of the well region partially and a body region formed in the well region under the contact opening.

REFERENCES:
patent: 6049104 (2000-04-01), Hshieh et al.
patent: 6153451 (2000-11-01), Hutter et al.
patent: 6165821 (2000-12-01), Boden et al.
patent: 6773977 (2004-08-01), Reynes et al.

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