Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-26
2004-04-27
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06727145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a fabrication method for a read only memory cell (ROM cell), and more particularly relates to a fabrication method for a post-process one-time programmable (OTP) read only memory cell (ROM cell).
2. Description of the Prior Art
In view of the programming process of the conventional read only memory product must be simultaneously performed in the manufacture process. When the manufacturer builds the product according to the order received from the customer, the actual amount of the product produced is usually larger than the order so as to avoid the short delivery of the product. However, it will cause excess product to storage in the depot after delivering and it will increase the manufacturing cost. Furthermore, the manufacturer could not immediately provide the goods of the programmed read only memory to customers because the read only memory product requires performing the programming process simultaneously in the manufacturing process.
Referring to FIG.
1
A and
FIG. 1B
, a conventional ROM cell array is shown as a schematic representation of a structure and a cross-section view, in accordance with prior techniques. As shown in the figures, a substrate
10
′ is a P type semiconductor and the semiconductor substrate
10
′ is ions-implanted to form a plurality of N type semiconductor-implanted regions
12
′ (as a bit line of the ROM cell) respectively to divide into a drain region and a source region. Following an oxide layer
14
′ and a polysilicon layer
16
′ are sequentially formed on the semiconductor substrate
10
′. The polysilicon layer
16
′ (as word line of the ROM cell) is used as the gate electrode of the ROM cell. The programming region of the ROM cell is positioned between those N type semiconductor-implanted regions
12
′, where signed regions
18
′ are defined. With such conventional read only memory one must simultaneously perform the programming process in the manufacture process.
Obviously, the main spirit of the present invention is to provide a method for fabricating a post-process OTP ROM cell, and then some disadvantages of well-known technology are overcome.
SUMMARY OF THE INVENTION
The primary object of the invention is to provide a method for fabricating a post-process one-time programmable (OTP) read only memory cell (ROM cell), wherein a sunken window-type isolating channel is formed by the oxide layer, which is positioned between the semiconductor-implanted regions and the polysilicon layer in the semiconductor substrate. After the manufacture process, the ROM cell can be programmed by applying a voltage thereon to penetrate the sunken window-type isolating channel.
Another object of the invention is to provide a method for fabricating a post-process OTP ROM cell, wherein a sunken window-type isolating channel is formed by the oxide layer, which is positioned between the semiconductor-implanted regions and the polysilicon layer in the semiconductor substrate. Due to the cross-section width of the window-type isolating channel is smaller than or equal to a cross-section width of the semiconductor-implanted regions and is positioned aligned within the cross-section width of those semiconductor-implanted regions, the structure of the present invention can effectively enhance the stability of the programming process.
A further object of the invention is to provide a method for fabricating a post-process OTP ROM cell. Without the require of simultaneously performing the programming process in the manufacture process, the manufacturers can instantaneously perform the programming process of the post-process OTP ROM cell of available goods after receiving the customer's order. This can enhance the maneuverability of the supply without the pressure from storing the large number of the stocks.
In order to achieve previous objects, the present invention provides a fabrication method for forming a post-process OTP ROM cell. The method comprises following essential steps. First, a semiconductor substrate is provided and the substrate is partially ion-implanted to form a plurality of semiconductor-implanted regions therein respectively to divide into a drain region and a source region. Then, a first oxide layer is formed on the semiconductor substrate and a portion of the first oxide layer is removed, where the portion is corresponding to those semiconductor-implanted regions. Following, a second oxide layer is conformably formed on the first oxide layer. Next, a polysilicon layer is formed on the second oxide layer and then the polysilicon layer is etched to be bar-positioned on the second oxide layer to use as the gate electrode of the ROM cell.
REFERENCES:
patent: 5532181 (1996-07-01), Takebuchi et al.
patent: 5666311 (1997-09-01), Mori
patent: 5946230 (1999-08-01), Shimizu et al.
patent: 6583490 (2003-06-01), Hagiwara et al.
Megawin Technology Co., Ltd.
Nhu David
Rosenberg , Klein & Lee
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