Method for fabricating polysilicon thin film transistor

Details Method for fabricating polysilicon thin film transistor Method for fabricating polysilicon thin film transistor

2001-10-01

2003-04-01

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S158000, C438S162000, C438S166000

Reexamination Certificate

active

06541323

ABSTRACT:

This application claims the benefit of Korean Application No. P2000-58678 filed on Oct. 6, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a method for fabricating a polysilicon TFT. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving electrical characteristics of the thin film transistor.
2. Discussion of the Related Art
In a conventional process for forming a polysilicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a plasma chemical vapor deposition (PCVD) method or a low pressure chemical vapor deposition (LPCVD) method. After the amorphous silicon layer has a thickness of about 500 Å (angstrom), it is recrystallized into a polysilicon layer by using a crystallization method. The crystallization method is generally classified into a laser annealing method, a solid phase crystallization (SPC) method, and a metal induced crystallization (MIC) method.
For the laser annealing method, an insulating substrate where an amorphous silicon layer is formed is heated to a temperature of about 250° C. An eximer laser beam then is applied to the amorphous silicon layer to form a polysilicon layer. For the SPC method, a heat-treatment is used to the amorphous silicon layer at a high temperature for a long time to form a polysilicon layer. For the MIC method, a metal layer is deposited on the amorphous silicon layer and the deposited metal is used for a crystallization seed. In case of the MIC method, a large scaled glass substrate can be used as an insulating substrate.
The laser annealing method has been widely used to form a polysilicon layer. In the laser annealing method, laser energy is provided for the amorphous silicon layer formed on the insulating substrate, thereby melting the amorphous silicon layer. Then, the melted amorphous silicon is transformed to polysilicon by a cooling process.
In case of the SPC method, a buffer layer is formed on a quartz substrate that can stand at a temperature higher than 600° C. The buffer layer serves to prevent spreading a contamination from the quartz substrate. Thereafter, an amorphous silicon layer is deposited on the buffer layer and is sufficiently heat-treated in a furnace at a high temperature so as to form a polysilicon layer. However, because the SPC method is performed at the high temperature, it is difficult to acquire a desired polysilicon phase.
In the process of SPC method, because polysilicon grains develop without a continuous directionability, the polysilicon layer may have an irregular surface. For a thin film transistor, a gate insulating layer covers the polysilicon layer. Therefore, if the polysilicon layer has the irregular surface, the gate insulating layer is also irregularly formed, thereby decreasing a breakdown voltage of the thin film transistor. In addition, size of the polysilicon grains formed by the SPC method is very irregular, thereby deteriorating electrical characteristics of a device adopting the polysilicon layer. Furthermore, the quartz substrate used for the SPC method is very expensive, thereby increasing a fabrication cost.
Unlike the SPC method that uses an expensive quartz substrate, the MIC method uses a relatively cheap glass substrate to form polysilicon. In case of using the MIC method, however, metal impurities may remain in the polysilicon network, thereby deteriorating the quality of the polysilicon layer. Accordingly, new methods have been developed to improve the MIC method.
A field effect metal induced crystallization (FEMIC) method is an example of the improved MIC method. In the FEMIC method, after a metal layer is deposited on a substrate, a high density direct current is applied to the metal layer to cause Joule heating. Because of the heated metal, an amorphous silicon formed on the heated substrate is crystallized into the polysilicon. At this point, the metal serves as a catalyzer and is referred as a catalytic metal.
FIGS. 1A
to
1
F illustrate a typical process of forming a polysilicon TFT according to the related art. The polysilicon TFT is a coplanar type TFT having a top gate structure. The FEMIC method is applied to form the polysilicon TFT.
In
FIG. 1A
, a first insulating layer
2
and an amorphous silicon layer
4
are sequentially deposited on a substrate
1
. The first insulating layer
2
is to protect the amorphous silicon layer
4
from alkali substances, which may be produced from the substrate
1
in later processes. After the amorphous silicon layer
2
is formed, a thin catalytic metal layer
5
is formed thereon. Nickel (Ni) is typically selected for the catalytic metal.
In
FIG. 1B
, a power source
6
applies a high density current to the catalytic metal layer
5
, thereby crystallizing the amorphous silicon layer
4
(shown in
FIG. 1A
) into a polysilicon layer
7
. After the crystallization process, the catalytic metal layer
5
is removed from the substrate
1
, and the polysilicon layer
7
is patterned into a polysilicon island
8
, as shown in FIG.
1
C.
In
FIG. 1D
, a second insulating layer
10
referred to as a gate insulating layer and a gate electrode
12
are sequentially formed on the polysilicon island
8
. Then, an ion doping is applied to the polysilicon island
8
, thereby dividing the polysilicon layer
8
into an active region
14
, a source region
16
, and a drain region
17
. The active region
14
is a pure silicon region, whereas the source and drain regions
16
and
17
are doped silicon regions. The active region
14
is centered between the source and drain regions
16
and
17
on the first insulating layer
2
, and the gate insulating layer
10
and the gate electrode
12
are disposed on the active region
14
.
Because the gate insulating layer
10
and the gate electrode
12
are patterned with the same mask in order to reduce the number of masks, they have the same shape. When the ion doping is applied to the polysilicon island
8
, the gate electrode
12
serves as an ion stopper to prevent a dopant from penetrating into the active region
14
. After the ion doping is finished, the polysilicon island
8
implements a specific electric characteristic, which varies with types of the dopant. If the dopant includes a Group III element such as B
2
H
6
that, the doped portion of the polysilicon island
8
becomes a p-type semiconductor. If the dopant includes a Group VI element such as PH
3
, the doped portion of the polysilicon island
8
becomes an n-type semiconductor. A proper dopant should be selected to satisfy the use of a device. After the dopant is applied onto the polysilicon island
8
, the dopant is activated.
In
FIG. 1E
, a third insulating layer
18
that serves as an interlayer insulating layer is formed to cover the gate electrode
12
, the active region
14
, and the source and drain regions
16
and
17
. A source contact hole
18
a
and a drain contact hole
18
b
are formed to pass through the third insulating layer
18
, thereby exposing the source and drain regions
16
and
17
, respectively.
In
FIG. 1F
, a source electrode
20
and a drain electrode
22
are formed on the third insulating layer
18
. The source and drain electrodes
20
and
22
electrically contact the source and drain regions
16
and
17
, respectively, through the source and drain contact holes
18
a
and
18
b
. Thereafter, a passivation layer
26
and a pixel electrode
28
are sequentially formed to cover the source and drain electrodes
20
and
22
. The passivation layer
26
has a pixel contact hole
26
a
that exposes a portion of the drain electrode
22
. The pixel electrode
28
electrically contacts the drain elelctrode
22
through the pixel contact hole
26
a.
In the conventional process of fabricating the polysilicon TFT, it is difficult for the catalytic metal layer
5
(shown in
FIG. 1A
) to have a uniform thickness. If the catalytic metal layer
5
has an irregu

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