Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-19
2001-11-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S232000, C438S252000
Reexamination Certificate
active
06319762
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The invention relates to a method for fabricating poly-spacers, more particularly, to a method for fabricating poly-spacers used in a semiconductor substrate.
b) Description of the Prior Art
Concerning flash memory in the submicron manufacturing process, the poly-spacer is widely used as a word line. However, there are some disadvantages in the conventional manufacturing process of poly-spacer word lines. The conventional technologies will be described herein with reference to the accompanying drawings.
The first conventional method for fabricating poly-spacer word lines in the flash memory cell is illustrated in FIG.
1
. The reference numerals
1
and
2
represent the gate of a flash memory and the periphery MOS (Metal-Oxide Semiconductor) sections respectively and are used to represent the same structures in the following description. As shown in
FIG. 1
, in the first conventional method for fabricating poly-spacer word lines, an undoped poly-spacer is first formed and then impurities (such as P-type or A-type) are implanted into the undoped poly-spacer by an ion implantation at zero degrees. Finally, the memory cell is thermally annealed in order that the lattice structure deteriorated in the ion implantation step can be recovered and the impurities can be activated. The poly-spacer word lines are thus formed.
However, using the first conventional method for fabricating poly-spacer word lines, impurities will not be implanted into the poly-spacers everywhere because ion implantation is performed at zero degrees. Therefore, generation of the depletion gate phenomenon is inevitable, which causes the threshold voltage V
t
, to drift and the reliability is thus deteriorated.
The second conventional method, as is illustrated in
FIG. 2
, makes some improvements over the first conventional method. This method is performed by the following steps: (1) forming an undoped polysilicon layer; (2) performing the ion implantation to the polysilicon layer twice at two different angles so as to prevent the depletion gate phenomenon; (3) forming poly-spacers by anisotropic dry etching.
However, the main drawback of the second conventional method is that the power control of the ion implantation needs to be very precise as the poly-spacer is thick. If the power is too low, impurities cannot be implanted into the poly-spacer with enough depth. On the contrary, if the power is too high, the implantation depth cannot be precisely controlled and the photoresist layer covering other sections may be burned out causing contamination in the word line channels.
The main difference between the third conventional method and the above-mentioned two methods is that instead of ion implanting impurities into the polysilicon layer after it is formed, the doped polysilicon layer in the third conventional method is formed by in-situ CVD (chemical vapor deposition) doping to prevent the generation of the depletion gate.
Although the third conventional method for fabricating poly-spacer word lines can achieve better quality in impurity and uniformity, the overall manufacturing process thereof is comparatively complicated when taking into consideration the integration of other periphery MOS sections. For example, after forming the doped polysilicon layer
3
, as shown in
FIG. 3A
, dry etching is performed to remove the undesired section of the polysilicon layer
3
and the poly-spacer word line is formed (FIG.
3
B). Then, the polysilicon layer is formed on the periphery MOS. For example, a lithography step and an etching step are utilized to form a cap layer
4
(FIG.
3
C). Subsequently, an undoped polysilicon layer
5
is formed (FIG.
3
D). Finally, a lithography step and an etching step are utilized to define a polysilicon layer on the periphery MOS.
In addition to the complicated manufacturing process, the thermal budget used in the third conventional method is quite high so that impurities in other diffusion layers are easily diffused again. Besides, reliability problems induced by over etching or incomplete etching due to the high aspect ratio of the poly-spacer exists.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a method for fabricating poly-spacer word lines having the advantages of: the depletion gate being eliminated, high reliability, a simple manufacturing process and a low thermal budget.
The method for fabricating poly-spacers in accordance with the invention comprises: forming an undoped first polysilicon layer on a semiconductor substrate; performing a first ion implantation with a first angle to implant impurities into the first polysilicon layer; performing a second ion implantation with a second angle to implant the impurities into the first polysilicon layer; forming a second polysilicon layer on the first polysilicon layer; and etching the first polysilicon layer and the second polysilicon layer to form spacers.
In addition, the invention provides a method for fabricating poly-spacers by which the poly-spacer word line and the polysilicon gate layer can be formed simultaneously. The method comprises: forming an undoped first polysilicon layer on a semiconductor substrate; performing a first lithography step to form a first photoresist layer covering sections of the first polysilicon layer which is not to be implanted with impurities; performing a first ion implantation with a first angle to implant impurities into the first polysilicon layer; performing a second ion implantation with a second angle to implant the impurities into the first polysilicon layer; removing the first photoresist layer; forming a second polysilicon layer on the first polysilicon layer; performing a second lithography step to form a second photoresist layer covering sections of the second polysilicon layer which is to be remained; etching the first polysilicon layer and the second polysilicon layer to form spacers; and removing the second photoresist layer.
REFERENCES:
patent: 5943576 (1999-08-01), Kapoor
patent: 6090653 (2000-07-01), Wu
patent: 6127236 (2000-10-01), Prall et al.
patent: 6130134 (2000-10-01), Chen
patent: 6236085 (2001-05-01), Kawaguchi et al.
Chen Jia-ren
Chuang Po-lung
Lai Yen-hung
Liaw Shiou-Han
Lo Yau-feng
Lindsay Jr. Walter L.
Martine & Penilla LLP
Niebling John F.
TSMC-Acer Semiconductor Manufacturing Corp.
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