Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Patent
1996-08-01
1998-08-18
Padgett, Marianne
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
438789, 438792, 438780, 427579, H05H 124, B05D 314, H01L 2102
Patent
active
057958335
ABSTRACT:
The present invention provides a method of fabricating passivation layers over closely spaced metal lines on a substrate. More particularly, the invention forms a three layer sandwich of passivation layers comprised of (1) a first thin plasma enhance silicon nitride (PE-SiN) layer; (2) a silicon oxide layer; and (3) a second silicon nitride layer. The method begins by forming closely spaced metal lines 20 over a substrate surface. A first silicon nitride layer 24 is formed using a low powered plasma enhanced chemical vapor deposition process, over the metal lines 20 and the substrate surface. A silicon oxide layer 28 is then formed over the first silicon nitride layer. A second nitride layer 32 is formed, using a plasma enhanced chemical vapor deposition process, over the silicon oxide layer 28. The method further includes forming an insulating layer 36 over the second nitride layer. The passivation layers of the invention is preferably formed over the top metal layer.
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Cheng Yao-Yi
Yu Chen-Hua
Ackerman Stephen B.
Padgett Marianne
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company Ltd
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