Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-07
2001-08-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S624000, C438S756000, C438S751000, C438S757000, C438S759000
Reexamination Certificate
active
06277725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a passivation layer on a metal pad. More particularly, the present invention relates to a method for fabricating a passivation layer on a metal pad in which the passivation layer protects the metal pad from damage.
2. Description of Related Art
In a conventional semiconductor manufacturing process metal pads are formed on a substrate; some metal pads are for wire bonding and others serve as a high reflectance material layer. After the metal pads are formed, a first silicon dioxide layer serving as a passivation layer is formed by high density plasma chemical vapor deposition to cover the metal pads, and a thickness of the first silicon dioxide layer is 5000 to 15000 Å. A chemical mechanical polishing process is performed to reduce the thickness of the first silicon dioxide layer. After the chemical mechanical polishing process, the thickness of the first silicon dioxide layer is 1500 to 2000 Å. Then, a portion of the first silicon dioxide layer is removed by dry etching to expose the metal pads, so that the residual first silicon dioxide layer remains only between the metal pads. A second silicon dioxide layer whose thickness is controlled precisely and a silicon nitride layer are formed in sequence over the substrate. After light passes through the second silicon dioxide layer and the silicon nitride layer, and is reflected from the metal pads serving as the high reflectance material layer, constructive interference is produced.
In the above process, a dishing effect occurs after the chemical mechanical polishing process and the first silicon dioxide layer is excessively removed during the dry etching process. As a result, the planarity of the semiconductor is poor. Furthermore, the surface of each of the metal pads is damaged during the dry etching process, so that reflectance of each of the metal pads is reduced.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a passivation layer on a metal pad in which the passivation layer protects the metal pad from damage.
As embodied and broadly described herein, the invention provides a method for fabricating a passivation layer on a metal pad. A conformal first silicon dioxide layer is formed on a substrate having a metal pad. A conformal first silicon nitride layer is formed on the first silicon dioxide layer, and then a second silicon dioxide layer is formed on the first silicon nitride layer by high density plasma chemical vapor deposition. The second silicon dioxide layer is planarized to expose the first silicon nitride layer. A portion of the first silicon nitride layer aligned over the metal pad is removed to expose the first silicon dioxide layer. A second silicon nitride layer is formed to cover the first silicon dioxide layer and the second silicon dioxide layer. In the above process, a thickness of the first silicon dioxide layer and a thickness of the second silicon nitride layer should be controlled precisely.
In the invention, the first silicon dioxide layer covers the metal pad, so that the surface of the metal pad is not damaged during the process. Therefore, reflectance of the metal pad is maintained. Additionally, constructive interference is produced after light passes through the first silicon dioxide layer and the second silicon nitride layer and is reflected from the metal pad because the thicknesses of the first silicon dioxide layer and the second silicon dioxide layer are controlled precisely. By controlling the thickness of the first silicon nitride layer and the chemical mechanical polishing process, the surface composed of the first silicon dioxide layer and the second silicon dioxide layer is planar.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5792705 (1998-08-01), Wang et al.
patent: 5851603 (1998-12-01), Tsai et al.
patent: 6030881 (2000-02-01), Papasouliotis et al.
Nguyen Ha Tran
Niebling John F.
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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