Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
1999-01-19
2001-09-18
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S460000, C438S424000, C438S780000, C438S958000
Reexamination Certificate
active
06291316
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a wafer-level process for fabricating a plurality of passivated semiconductor devices, and more particularly relates to a simpler, cheaper and environmentally friendly wafer-level process for fabricating a plurality of passivated low- and high-voltage semiconductor devices.
The manufacturing process of a semiconductor device, such as a rectifier, can be roughly divided into four stages; that is, junction formation, junction exposure, junction passivation and contact formation.
The known process of the junction formation stage comprises doping a wafer by diffusion to provide a p-n layer suitable for the intended application.
The known process of the junction exposure stage comprises cutting a plurality of grooves to form a plurality of chips. The cutting operation may be performed by a disc sass having a blade that is adapted to cut partly through the thickness of the wafer. Then, the wafer is fractured along the lines of the cut into the individual chips. Alternatively, the Cutting operation can also be performed by a sandblasting operation wherein stainless steel resistant elements are bonded in the shape of the desired chips onto the surface of the wafer. Then a blast of sand wears grooves through the wafer around the edges of the resistant elements to divide the wafer into the desired chips. Since the handling of the individual chips in the subsequent processes is cumbersome and expensive, several wafer-level processes are proposed. U.S. Pat. No. 4,904,610 provides a process which comprises the steps of mounting the wafer on a substrate by an intervening layer of adhesive and cutting a multiplicity of grooves in the mounted wafer to form a plurality of chips wherein the grooves extend entirely through the wafer and partly through the layer of adhesive without extending into the substrate. The process of U.S. Pat. No. 4,904,610 requires a further step of using a solvent (hazardous and environmentally harmful) to remove the layer of adhesive. Besides, the way that discrete chips are bonded onto a substrate by a layer of adhesive cannot always provide a firm connection among the chips as that of a true wafer. The widely adapted wafer-level process in the junction exposure stage comprises photolithographic steps to etch grooves in the wafer to expose the p-n junction of the p-n layer wherein the grooves are partly through the wafer and have a depth that is enough to expose the p-n junction. However, the photolithographic steps are numerous and complex which in turn affect reliability.
In the junction passivation stage, the process of U.S. Pat. No. 4,904,610 comprises the step of applying a silicone resin onto the grooved wafer to fill the grooves with the resin. The silicone resin covers the surfaces of the chips in addition to the grooves, and thus after the resin is cured a further step of removing the resin covering the surfaces of the chips is needed. Another conventional process uses photolithography to apply glass into the grooves to passivate the junctions. However, as discussed above, the photolithographic steps are cumbersome and complex.
The widely adapted process in the contact formation stage comprises photolithographical etching contact which is cumbersome and complex. The process of U.S. Pat. No. 4,904,610 forms the contacts (electrodes) by a three-step plating operation at the beginning of the whole process, and the whole surface of the wafer is gold-plated after the three-step plating operation. In the subsequent steps of the process of U.S. Pat. No. 4,904,610, the gold plating on the portions to be grooved will be removed and thus wasted.
Therefore, a wafer-level process, for fabricating passivated low- and high-voltage semiconductor devices, that is simpler, cheaper, environmentally friendly and can avoid the shortcomings of the mentioned prior art is needed.
SUMMARY OF THE INVENTION
An objective of the invention is to provide a wafer-level process, for fabricating a plurality of passivated semiconductor devices, that can eliminate part of or all the steps of photolithographic steps.
Another objective of the invention is to provide a true wafer-level process that is simpler, cheaper and more environmentally friendly than the process of U.S. Pat. No. 4,904,610.
According to the process embodying the present invention, in the junction exposure stage, a cutting step to form a plurality of grooves to expose the p-n junctions formed in a wafer is provided wherein each of the grooves extends partly through the wafer and has a depth that is enough to expose the p-n junctions. To eliminate the cumbersome steps of photolithography and the use of an adhesive layer proposed in U.S. Pat. No. 4,904,610, the cutting step according to one embodiment of the present invention can be performed by using a disc saw having a blade or by a sandblasting operation. The sawing operation according to the present invention is different from that of prior art. Instead of cutting a certain depth through the wafer and fracturing the wafer along the lines of the Cult into individual chips, the sawing operation according to the present invention just cuts a depth, through the wafer, that is enough to expose the p-n junctions. Besides, the sandblasting operation according to the present invention does not divide the wafer into individual chips as taught by prior art, but forms grooves extending partly through the wafer and having depths enough to expose the p-n junctions by controlling the time of the sandblasting operation.
To further eliminate the complex photolithographic steps or the additional step of removing the passivating material covering the surfaces of the chips needed in the process of U.S. Pat. No. 4,904,610, the process of the junction passivation stage, according to another embodiment of the present invention comprises the step of screen printing a screen-printable passivating material into the grooves, or the step of pin dispensing a pin-dispensable passivating material into the grooves wherein the passivating material is directly applied into the grooves only, and thus the process of the junction passivation stage is greatly simplified.
To form contacts of the devices, the process according to a further embodiment of the present invention comprises the steps, before cutting the grooves, of plating a first nickel plate on the surface of the wafer and sintering the first nickel plate as well as the steps, after the junction passivation stage of plating a second nickel plate on the surface of the sintered first nickel plate and plating a gold plate on the surface of the second nickel plate. The above process is simpler than the conventional photolithographic contact etching process and is more cost-effective than the process of U.S. Pat. No. 4,904,610.
REFERENCES:
patent: 4829014 (1989-05-01), Yerman
patent: 4904610 (1990-02-01), Shyr
patent: 5482887 (1996-01-01), Duinkerken et al.
Knowles Christopher Michael
Lin Tung-Chieh
Lin Yih-Yin
Nelson William John
O'Rourke Richard Sean
Berezny Neal
Fahmy Wael
General Semiconductor of Taiwan, LTD
Mayer Fortkort & Williams PC
Williams Esq. Karin L.
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