Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-13
2003-09-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S239000, C438S241000
Reexamination Certificate
active
06620685
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of fabricating the same and, more particularly, to a dynamic random access memory (DRAM) having a metal plug.
2. Description of the Related Art
As the degree of integration of semiconductor memory devices such as a dynamic random access memory (DRAM) device increases, design rules and fabricating margins are generally reduced. Even with such reduction, capacitor capacitance should be maintained to operate the DRAM devices.
To provide a suitable capacitance, a capacitor having a three-dimensional configuration has been developed for increasing the capacitance per unit area. In such a configuration, a trench type capacitor, a stack type capacitor, and a trench and stack combined type capacitor have been proposed. The stack type capacitor is widely used because it utilizes conventional fabrication technology. In particular, a stack type capacitor having a capacitor over bit line (COB) is most widely used so as to easily increase the effective area of the capacitor.
Generally, the stack type capacitor has a storage electrode pad (or buried contact plug) formed of a doped polysilicon layer, and the pad is usually shaped in a narrow and long pillar. The resistance between a storage electrode of the capacitor formed over the storage electrode pad and a source in a semiconductor substrate is high, and read/write data transmitting therethrough can be delayed. Additionally, as dopants of the doped polysilicon diffuse to the semiconductor substrate (which is called an out-diffusion phenomena), an efficient channel distance of a transistor formed between a source and a drain of the semiconductor substrate is reduced, thereby deteriorating operating characteristics of the transistor.
An inter-layer pathway, referred to in the art as a “plug” or “stud” is generally included in highly integrated devices for electrically coupling between the various active devices and transmission lines. To assist in aligning a plug, “landing pads” is formed in lower parts to serve as a target for the plugs passing from the upper layer. The landing pads are coupled to an underlying circuit or interconnect, and the landing pads are typically formed of metal. Thus, the process for fabricating the plug or stud is complex. For example, when the doped polysilicon layer is used as a storage electrode pad of the capacitor, the landing pad and the plug cannot be simultaneously fabricated with the doped polysilicon layer.
Accordingly, a need exists for an improved method for forming a semiconductor memory device having a metal plug or a landing pad. A need also exists for a DRAM device having a high aspect ratio with reference to the height of a hole as compared to its width for minimizing signal transmission delay.
SUMMARY OF THE INVENTION
A semiconductor memory device is provided, which includes a first insulating layer having a gate electrode on a semiconductor substrate; a second insulating layer formed on the first insulating layer, the second insulating layer having bit lines covered with bit line isolation layers, buried contact plugs formed between the bit lines, and a first metal contact plug connected to the semiconductor substrate through the first insulating layer; a silicon nitride layer on the second insulating layer; and a third insulating layer formed on the silicon nitride layer, the third insulating layer having a second metal contact plug connected to the first metal contact plug through the silicon nitride layer.
According to an embodiment of the present invention, the second insulating layer further includes a first landing stud connected to the gate electrode through the first insulting layer. The bit lines include a direct contact plug under one of the bit line. The first landing stud is simultaneously formed with the direct contact plug.
According to an embodiment of the present invention, the second insulating layer further includes a second landing stud on the first landing stud. The second landing stud is larger in surface area than the first landing stud. The first metal contact plug and the buried contact plugs are simultaneously formed with an electrical conducting material. The electrical conducting material includes tungsten (W). The third insulating layer further includes a metal-insulator-metal capacitor on the buried contact plug.
A method of fabricating a semiconductor memory device is also provide, which includes the steps of: forming a gate electrode on a silicon substrate, the silicon substrate being divided into a cell area and a peripheral area, and the gate electrode having a gate and a gate spacer being covered with the gate; forming a first inter-layer dielectric layer (ILD
1
) on the silicon substrate having the gate electrode; forming a cell pad poly between the gate electrodes in the cell area; forming a direct contact plug (DC) on the cell pad poly in the cell area, and a first landing stud on the gate in the peripheral area; forming a bit line on the DC in the cell area and a second landing stud on the first landing stud, the bit line being covered with a bit line isolation layer; forming a second inter-layer dielectric layer (ILD
2
) on the ILD
1
having the bit line to cover the bit line isolation layer; forming a silicon nitride layer on the ILD
2
; patterning the silicon nitride layer; etching out a portion of the ILD
2
in the cell area using the patterned silicon nitride layer and the bit line isolation layer as etching blocking layers until the cell pad poly is exposed, and simultaneously etching out a portion of the ILD
2
and a portion of the ILD
1
in the peripheral area using the patterned silicon nitride layer; and simultaneously forming a plurality of buried contact plugs in the cell area and a first metal contact plug in the peripheral area by filling electrically conducting material to the etching portions of the ILD
1
and ILD
2
.
According to an embodiment of the present invention, the cell pad poly is impurity doped polysilicon. The DC and the first landing stud include tungsten (W). The bit line and the second landing stud include tungsten (W). The plurality of buried contact plugs and the first metal contact plug are formed of tungsten (W). The silicon nitride layer is formed of Si
3
N
4
.
According to an embodiment of the present invention, the method further includes the steps of: forming a third inter-layer dielectric layer (ILD
3
) on the silicon nitride layer; patterning the ILD
3
to expose the buried contact plug; and forming a metal-insulator-metal (MIM) capacitor on the buried contact plug; planarizing the ILD
3
before forming the patterning the ILD
3
.
According to an embodiment of the present invention, the step of forming the MIM capacitor includes the steps of: forming a storage electrode on the silicon nitride layer; forming a insulating layer on the storage electrode; and forming a floating electrode on the insulating layer. The storage electrode is formed of tungsten (W). The method further includes the steps of: forming a fourth inter-layer dielectric layer (ILD
4
) on the ILD
3
having the MIM capacitor; patterning a portion of ILD
4
and a portion of ILD
3
to expose the MC
0
, patterning a portion of the ILD
4
, a portion of ILD
3
, and a portion of ILD
2
to expose the second landing stud, and patterning a portion of the ILD
4
to expose the MIM capacitor; and forming a second metal contact plug to connect to the MC
0
, the second landing stud, and MIM capacitor. The second metal contact plug is formed of tungsten.
REFERENCES:
patent: 6143601 (2000-11-01), Sun
patent: 6258649 (2001-07-01), Nakamura et al.
patent: 6329681 (2001-12-01), Nakamura et al.
F. Chau & Associates LLP
Nelms David
Samsung Electronics Co. LTD
Tran Long
LandOfFree
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