Method for fabricating NROM memory cells with trench...

Details Method for fabricating NROM memory cells with trench... Method for fabricating NROM memory cells with trench...

2007-04-17

2007-04-17

Hoang, Quoc (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S589000, C257S330000, C257SE21428, C257SE29321

Reexamination Certificate

active

11006049

ABSTRACT:
An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).

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Eitan, B, et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.

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