Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-11
2004-08-10
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S264000, C438S275000
Reexamination Certificate
active
06773992
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an erasable nonvolatile semiconductor memory device such as an EPROM device, an EEPROM device, or a flash memory device. More particularly, it relates to a method for fabricating a nonvolatile semiconductor memory device having a logic circuit portion, including a peripheral circuit and the like, merged therein.
A description will be given herein below to a conventional method for fabricating a nonvolatile semiconductor memory device with reference to the drawings.
FIGS. 9A
,
9
B,
9
C,
10
A,
10
B,
10
C,
11
A, and
11
B show cross-sectional structures of a nonvolatile semiconductor memory device in the individual process steps of the conventional fabrication method therefor.
First, as shown in
FIG. 9A
, dielectric isolation films
102
are formed in a semiconductor substrate
101
made of P-type silicon and having a memory circuit portion
1
B and a logic circuit portion
2
B composing a peripheral circuit for the memory circuit portion
1
B. Then, a protective insulating film
103
with a thickness of about 20 nm is formed over the entire surface of the semiconductor substrate
101
.
Subsequently, a first resist pattern
201
having an opening corresponding to the memory circuit portion
1
B of the semiconductor substrate
101
and to the region of the logic circuit portion
2
B of the semiconductor substrate
101
to be formed with an N-type MOS transistor is formed on the protective insulating film
103
. By using the first resist pattern
201
as a mask, boron ions are implanted into the semiconductor substrate
101
so that a first P-well
104
is formed.
Next, as shown in
FIG. 9B
, a second resist pattern
202
having an opening corresponding to the N-type MOS transistor formation region of the logic circuit portion
2
B is formed on the protective insulating film
103
. By using the second resist pattern
202
as a mask, boron ions are implanted for threshold voltage control so that a second P-well
105
is formed in the N-type MOS transistor formation region of the logic circuit portion
2
B. Thus, the second P-well
105
is formed by two steps of boron ion implantation.
Next, as shown in
FIG. 9C
, a third resist pattern
203
having an opening corresponding to the region of the logic circuit portion
2
B to be formed with a P-type MOS transistor is formed on the protective insulating film
103
. By using the third resist pattern
203
as a mask, phosphorus ions are implanted into the semiconductor substrate
101
so that an N-well
106
is formed in the P-type MOS transistor formation region of the logic circuit portion
2
B.
Next, as shown in
FIG. 10A
, the protective insulating film
103
is removed. Then, a first insulating film
107
with a thickness of about 10 nm, a first polysilicon film
108
, and a second insulating film
109
composed of a multilayer structure of a silicon dioxide and a silicon nitride are grown successively on the semiconductor substrate
101
.
Next, as shown in
FIG. 10B
, a fourth resist pattern
204
having an opening corresponding to the logic circuit portion
2
B is formed on the second insulating film
109
. By using the fourth resist pattern
204
as a mask, etching is performed sequentially with respect to the second insulating film
109
, the first polysilicon film
108
, and the first insulating film
107
, thereby exposing the logic circuit portion
1
B of the semiconductor substrate
101
.
Next, as shown in
FIG. 10C
, the fourth resist pattern
204
is removed. Then, a third insulating film
110
and a second polysilicon film
111
are grown successively over the second insulating film
109
in the memory circuit portion
1
B and the semiconductor substrate
101
in the logic circuit portion
2
B.
Next, as shown in
FIG. 11A
, a fifth resist pattern
205
including a pattern for forming a gate electrode structure in the memory circuit portion
1
B is formed on the second polysilicon film
111
. By using the fifth resist pattern
205
, the films grown successively on the semiconductor substrate
101
are patterned into the gate electrode structure. Specifically, a tunnel insulating film
107
a
is formed from the first insulating film
107
, a floating fate
108
a
is formed from the first polysilicon film
108
, a capacitance insulating film
112
is formed from the second and third insulating films
109
and
110
, and a control gate
111
a
is formed from the second polysilicon film
111
.
Next, as shown in
FIG. 11B
, the fifth resist pattern
205
is removed. Then, a sixth resist pattern
206
including a pattern for forming a gate electrode in the logic circuit portion
2
B is formed on the second polysilicon film
111
covering the logic circuit portion
2
B. By using the sixth resist pattern
206
as a mask, etching is performed sequentially with respect to the second polysilicon film
111
and the third insulating film
110
, thereby forming a gate electrode
111
b
from the second polysilicon film
111
and forming a gate insulating film
110
b
from the third insulating film
110
.
Thus, the conventional method for fabricating a nonvolatile semiconductor memory device has performed the implantation of boron ions into the N-type MOS transistor formation region of the logic circuit portion
2
B simultaneously with the formation of the first P-well
104
. Then, a thermal oxidation process at a temperature of about 850° C. to 950° C. is normally performed during the formation of the first insulating film
107
for forming the tunnel insulating film
107
a
shown in FIG.
10
A. The formation of the first polysilicon film
111
for forming the floating gate
108
a
employs a low-pressure CVD process which requires a heating temperature of about 600° C. to 700° C.
Due to the thermal budget, an impurity concentration profile is diffused in the first P-well
104
, in the second P-well
105
, and in the N-well
106
so that the problems of a degraded dielectric isolation property and an increased drain-junction capacitance occur. In particular, a MOS transistor contained in the logic circuit portion
2
B is required to have an excellent dielectric isolation property and a high drain-junction breakdown voltage so that it is seriously affected by the diffused impurity concentration profile in the wells
104
,
105
, and
106
. If the MOS transistor is required to be further miniaturized, influence not only on the dielectric isolation property but also on a short-channel effect cannot be ignored.
As recent CMOS fabrication processes have been performed at lower temperatures, ion implantation with a high acceleration energy has been used more frequently to form each of the wells
105
and
106
. If such ion implantation with a high acceleration energy is performed, a contaminant containing heavy metal and the like are likely to enter the semiconductor substrate
101
so that the problem of the degraded gate insulating film
110
B also occurs.
To prevent the contaminant from entering the semiconductor substrate
101
, the protective insulating film
103
is formed normally on the surface of the semiconductor substrate
101
, as shown in FIG.
9
A. However, the protective insulating film
103
has its upper portion graded during the removal of each of the resist patterns
201
,
202
, and
203
and the thickness thereof is gradually reduced. Consequently, the protective insulating film
103
cannot sufficiently perform the function of protecting the semiconductor substrate
101
. These problems are increasingly aggravated as elements are further miniaturized to an extent that they cannot be cancelled out any more merely by reducing the number of process steps and cost.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to solve the foregoing conventional problems and prevent, in a semiconductor device having a memory circuit portion and a logic circuit portion merged therein, a thermal budget resulting from process steps for fabricating the memory circuit portion from affecting the well regions of the logic circuit portion. A second o
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Trinh Michael
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