Method for fabricating nonvolatile semiconductor memory device

Details Method for fabricating nonvolatile semiconductor memory device Method for fabricating nonvolatile semiconductor memory device

1998-09-23

2000-02-29

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438286, 438305, H01L 21336

Patent

active

060308699

ABSTRACT:
A method for fabricating a nonvolatile semiconductor memory device having a stacked gate portion, including a tunnel insulating film, a floating gate electrode, a capacitive insulating film and a control gate electrode, formed over a p-type Si substrate. In the p-type Si substrate, n.sup.++ source/drain layers and n.sup.+ source/drain layers, each layer containing arsenic, are formed. In the drain region, an n.sup.- drain layer, containing phosphorus and overlapping with an entire edge of the stacked gate portion in the gate width direction, and a p layer surrounding the bottoms of the n.sup.+ and the n.sup.- drain layers are provided. In such a structure, an electric field applied between the floating gate electrode and the drain is weakened and the drain-disturb characteristics are improved during writing.

REFERENCES:
patent: 5712814 (1998-01-01), Fratin et al.
patent: 5780893 (1998-07-01), Sugaya
patent: 5780902 (1998-07-01), Komuro
Y. Ohshima et al., "Process and Device Technologies for 16Mbit EPROMs with Large-Tilt-Angle Implanted P-Pocket Cell", 1990 IEEE IEDM, pp. 95-98, 1990.
H. Kume et al., "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure", 1987 IEEE IEDM, pp. 560-563, 1987.

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