Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-08-08
2006-08-08
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S954000
Reexamination Certificate
active
07087487
ABSTRACT:
A method, for fabricating a semiconductor device including a memory region and a logic circuit region including a periphery circuit, includes: forming sidewall-like control gates on both side surfaces of a first conductive layer at least in a memory region with an ONO film interposed therebetween, respectively; patterning a first conductive layer in a logic circuit region and thereby forming a gate electrode of a MOS transistor; forming a second insulating layer above the control gates; applying anisotropic etching to the second insulating layer, and thereby at least partially exposing the control gates; and on the exposed surfaces of the control gates, forming a silicide layer.
REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6191441 (2001-02-01), Aoki
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 6531350 (2003-03-01), Satoh
patent: 2002/0100929 (2002-08-01), Ebina et al.
patent: 2002/0127805 (2002-09-01), Ebina et al.
patent: 2003/0054610 (2003-03-01), Ebina et al.
patent: 2003/0057505 (2003-03-01), Ebina et al.
patent: 2003/0058705 (2003-03-01), Ebina et al.
patent: 2003/0060011 (2003-03-01), Ebina et al.
patent: 7-161851 (1995-06-01), None
patent: 2978477 (1999-09-01), None
patent: 2001-156188 (2001-06-01), None
Chen, et al., “A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN),” 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.
Chang, et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Hayashi, et al., “Twin MONOS Cell with Dual Control Gates,” 2000 Symposium on VLSI Technology Digest of Technical Papers (2 pages).
Harness & Dickey & Pierce P.L.C.
Nhu David
LandOfFree
Method for fabricating nonvolatile memory device and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating nonvolatile memory device and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating nonvolatile memory device and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3693217