Method for fabricating non-volatile storage with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S129000, C438S379000, C257SE21422, C257SE21691

Reexamination Certificate

active

08062944

ABSTRACT:
A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates.

REFERENCES:
patent: 5877980 (1999-03-01), Mang
patent: 5936887 (1999-08-01), Choi
patent: 5990514 (1999-11-01), Choi
patent: 6044017 (2000-03-01), Lee
patent: 6093605 (2000-07-01), Mang
patent: 6246607 (2001-06-01), Mang
patent: 6434038 (2002-08-01), Ohno
patent: 6677199 (2004-01-01), Chang
patent: 6760253 (2004-07-01), Kamei
patent: 6845042 (2005-01-01), Ichige
patent: 7061040 (2006-06-01), Shih
patent: 7075823 (2006-07-01), Harari
patent: 7164168 (2007-01-01), Forbes et al.
patent: 7636260 (2009-12-01), Higashitani
patent: 7781286 (2010-08-01), Higashitani
patent: 7808826 (2010-10-01), Higashitani
patent: 2003/0094635 (2003-05-01), Yaegashi
patent: 2004/0012988 (2004-01-01), Kranister et al.
patent: 2005/0072999 (2005-04-01), Matami et al.
patent: 2005/0180186 (2005-08-01), Lutze
patent: 2005/0199939 (2005-09-01), Lutze
patent: 2005/0242377 (2005-11-01), Eguchi
patent: 2006/0039230 (2006-02-01), Kurata
patent: 2006/0108628 (2006-05-01), Hung
patent: 2006/0120155 (2006-06-01), Sato
patent: 2006/0145241 (2006-07-01), Forbes
patent: 2007/0138535 (2007-06-01), Higashitani
patent: 2007/0141780 (2007-06-01), Higashitani
patent: 2007/0252209 (2007-11-01), Yamazaki
patent: 2008/0160680 (2008-07-01), Yuan
Choi, “A triple polysilicon stacked flash memory cell with wordline self-boosting programming,” 1997 IEEE, pp. 283-286.
Choi, “A novel booster plate technology in high density NAND flash memories for voltage scaling-down and zero program disturbance,” 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 238-239.
Kim, “Fast parallel programming of multi-level NAND flash memory cells using the booster-line technology,” 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 65-66.
Satoh, “A novel channel boost capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4Gbit NAD Flash memories,” 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 108-109.
Office Action dated Mar. 4, 2009, U.S. Appl. No. 11/767,647, filed Jun. 25, 2007.
Response to Office Action dated Apr. 7, 2009, U.S. Appl. No. 11/767,647, filed Jun. 25, 2007.
Office Action dated Jun. 17, 2009, U.S. Appl. No. 11/767,647, filed Jun. 25, 2007.
Response to Office Action dated Jul. 1, 2009, U.S. Appl. No. 11/767,647, filed Jun. 25, 2007.
Notice of Allowance and Fee(s) Due, U.S. Appl. No. 11/767,647, filed Jun. 25, 2007.
Office Action dated Apr. 22, 2009, U.S. Appl. No. 11/767,652, filed Jun. 25, 2007.
Response to Office Action dated May 12, 2009, U.S. Appl. No. 11/767,652, filed Jun. 25, 2007.
Office Action dated Sep. 17, 2009, U.S. Appl. No. 11/767,652, filed Jun. 25, 2007.
Response to Office Action dated Dec. 17, 2009, U.S. Appl. No. 11/767,652, filed Jun. 25, 2007.
Office Action dated Mar. 16, 2010, U.S. Appl. No. 11/767,652, filed Jun. 25, 2007.
Response to Office Action dated Apr. 12, 2010, U.S. Appl. No. 11/767,652, filed Jun. 25, 2007.
Notice of Allowance and Fee(s) Due dated Jun. 4, 2010, U.S. Appl. No. 11/767,652, filed Jun. 25, 2007.
Restriction Requirement dated Mar. 23, 2009, U.S. Appl. No. 11/767,661, filed Jun. 25, 2007.
Response to Restriction Requirement dated Apr. 10, 2009, U.S. Appl. No. 11/767,661, filed Jun. 25, 2007.
Office Action dated Jul. 8, 2009, U.S. Appl. No. 11/767,661, filed Jun. 25, 2007.
Response to Office Action dated Jul. 8, 2009, U.S. Appl. No. 11/767,661, filed Jun. 25, 2007.
Office Action dated Dec. 30, 2009, U.S. Appl. No. 11/767,661, filed Jun. 25, 2007.
Response to Office Action dated Mar. 30, 2010, U.S. Appl. No. 11/767,661, filed Jun. 25, 2007.
Notice of Allowance and Fee(s) Due dated Apr. 19, 2010, U.S. Appl. No. 11/767,661, filed Jun. 25, 2007.
International Search Report & The Written Opinion of the International Searching Authority dated Sep. 25, 2008, International Application No. PCT.US2008/068048 filed Jun. 24, 2008.
International Preliminary Report on Patentability dated Jan. 5, 2010, International Application No. PCT/US2008/068048 filed Jun. 24, 2008.

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