Method for fabricating non-volatile memory

Details Method for fabricating non-volatile memory Method for fabricating non-volatile memory

2006-07-04

2006-07-04

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S157000, C438S283000, C438S287000, C438S288000, C438S304000

Reexamination Certificate

active

07071061

ABSTRACT:
A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every two stacked gate structures. An oxide layer is formed on the sidewalls of the first gate. A portion of the second dielectric layer not covered by the stacked gate structures is removed. A third dielectric layer is further formed on the substrate. A second conductive layer is formed over the substrate, and a portion thereof to form second gates. The second gates and the stacked gate structures form a column of memory cells. A source region and a drain region are formed in the substrate adjacent to two sides of the column of memory cells.

REFERENCES:
patent: 5930631 (1999-07-01), Wang et al.
patent: 6524915 (2003-02-01), Kim et al.
patent: 6580120 (2003-06-01), Haspeslagh
patent: 2005/0224858 (2005-10-01), Hung et al.
patent: 93125069 (2006-02-01), None

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