Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-03-11
2004-12-07
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000
Reexamination Certificate
active
06828197
ABSTRACT:
This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 092129733 filed in TAIWAN on Oct. 27, 2003, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a non-volatile memory, and more particularly to a method of fabricating a nitride read-only memory wherein the memory region is integrated with the peripheral circuit region.
2. Description of the Related Art
In the non-volatile memory industry, the development of nitride read-only memory started in 1996. Nitride read only memory is a semiconductor device for data storage. It is composed of a plurality of memory cells, each comprising a MOS transistor and an ONO gate dielectric layer. Since the silicon nitride layer in the ONO gate dielectric layer is highly dense, hot electrons can be trapped in the silicon nitride layer by way of tunneling through the MOS transistor, in order to store data. The new non-volatile memory technology utilizes oxide-nitride-oxide (ONO) gate dielectric and known mechanisms of program and erase to create two separate bits per cell. Thus, the NROM bit size is half the cell region. Since silicon die size is a main element in cost structure, it is apparent why the NROM technology is considered an economical breakthrough.
Although nitride read only memory has the advantage of two-bit multi-storage function, a simpler manufacturing process than similar products, and these widely welcomed by the market, the semiconductor industry is more and more orienting itself toward the development of system on chip (SOC) products to allow a single chip to comprise multiple memory and peripheral circuits. In U.S. Pat. No. 5,908,311, a method of forming peripheral circuits comprising flash ROM is disclosed. Based on different characteristics and applications of nitride read only memory and flash ROM, it is important to develop a system-on-chip integrating NROM with peripheral circuits.
SUMMARY OF THE INVENTION
An object of the invention is to provide a method of fabricating a nitride read-only memory, wherein the memory region is integrated with the peripheral circuit region to provide simplified manufacture and high yield.
The above objects are accomplished by providing a method of fabricating a nitride read-only memory comprising disposing a polysilicon layer as word lines in the memory region to serve as an insulator polishing stop layer formed in the first shallow trenches in the peripheral region by disposing an oxide layer, wherein the insulator is simultaneously formed between polysilicon structures in the memory array region to prevent reaction with metal such as cobalt during salicidation of the polysilicon. An ONO layer is formed on the sidewalls of the shallow trenches to avoid STI corner recess and dislocation of the STI profile deformation during thermal process. The method of the present invention comprises providing a semiconductor substrate, including a memory region and a peripheral circuit region therein growing a pad oxide on the semiconductor substrate forming a plurality of parallel buried diffusion regions as bit lines in the memory region; forming a first shallow trench and a second shallow trench in the peripheral circuit region; conformally forming an ONO film on the semiconductor substrate depositing a polysilicon layer on the ONO film to fill the first shallow trenches and the second shallow trench patterning the polysilicon layer to define a plurality of polysilicon structures to serve as word lines having gaps therein, in the memory region so as to remove the polysilicon filled in the first shallow trenches and leave the polysilicon layer filled in the second shallow trench in the peripheral circuit region forming an insulator in the first shallow trenches and the gaps between the word lines planarizing the insulator to leave shallow trench isolations in the first shallow trenches between the word lines, selectively etching the polysilicon structures and the ONO layer to expose the semiconductor substrate between the first shallow trenches and implanting dopants into the substrate between the first shallow trenches to define the well regions. The bit lines are formed by implanting N-type ions such as Phosphorous or Arsenic into the substrate, the gate dielectric layer is formed with the ONO layer, and the word lines are formed with polysilicon.
REFERENCES:
patent: 5908311 (1999-06-01), Chi et al.
patent: 6610586 (2003-08-01), Liu
Macronix International Co. Ltd.
Tsai H. Jey
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