Method for fabricating narrow channel field effect transistors h

Details Method for fabricating narrow channel field effect transistors h Method for fabricating narrow channel field effect transistors h

1996-12-27

1998-06-16

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438564, H01L 21336

Patent

active

057669988

ABSTRACT:
An improved reverse self-aligned FET having subquarter-micrometer channel lengths, shallow junction depths, and silicide source/drain contacts was achieved. The method for fabricating the FET includes forming a titanium layer, an N.sup.+ doped first polysilicon layer, and a silicon nitride layer over the device areas. A photoresist mask having first openings with minimal feature size is formed over the device areas where gate electrodes are desired. Non-volatile polymer sidewall spacers are formed on the side-walls of the first openings to extend the resolution limit of the photoresist. The sidewalls and photoresist are used as a mask to etch the silicon nitride layer, the first polysilicon layer, and the titanium layer to the substrate to form second openings (FET channel openings) where the gate electrodes are to be formed. A gate oxide is grown on the substrate in the channel openings, and a threshold-voltage implant and an anti-punchthrough implant are carried out in the channel openings, and then an N.sup.+ doped second polysilicon layer is patterned to form the gate electrodes over the gate oxide. The reverse self-aligned FET is then completed by carrying out subsequent thermal cycles to out-diffuse the N.sup.+ dopant from the first polysilicon layer through the titanium layer to form shallow source/drain junctions aligned to the gate electrodes.

REFERENCES:
patent: 5175118 (1992-12-01), Yoneda
patent: 5196357 (1993-03-01), Boardman et al.
patent: 5268317 (1993-12-01), Schwalke et al.
patent: 5545579 (1996-08-01), Liang et al.

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