Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-23
2002-02-19
Booth, Richard (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S303000, C438S306000, C438S307000, C257S408000, C257S396000
Reexamination Certificate
active
06348390
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates the fabrication process of semiconductor devices, and more specifically, to a method for fabricating metal oxide semiconductor field effect transistors (MOSFETs) with a recessed self-aligned silicide contact and extended source/drain junctions.
BACKGROUND OF THE INVENTION
From the birth of the first integrated circuit at 1960, the number of devices on a chip has grown in an explosive increasing rate. The progress of the semiconductor integrated circuits has step into ULSI (ultra large scale integration) level or even higher level after almost four decades of developments. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. Integrated circuits devices like transistors, capacitors, and connections must be greatly narrowed accompanying with the advancement. The increasing packing density of integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within smaller area without influencing the characteristics and the operations of the integrated circuits. The demands on high packing density, low heat generation, and low power consumption devices with a good reliability and a long operation life must be maintained without any degradation in the function. These achievements are expected to be reached with the simultaneous developments and advancements in the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies, namely the big five key aspects of semiconductor manufacturing. The continuous increase in the packing density of the integration circuits must be accompanied with a shrinking minimum feature size. With present semiconductor manufacturing technology, the processes with a generally one-third micrometer in size is widely utilized. For making the next generation devices, the technologies focusing mainly on one-tenth micrometer or even nanometer sizes are highly demanded.
Transistors, or more particularly metal oxide semiconductor field effect transistors (MOSFET), are the most important and frequently employed devices in the integrated circuits with the high performance. However with the continuous narrowing of device size, the sub-micron scale MOS transistors have to face so many risky challenges. As the MOS transistors become narrower and thinner accompanying with shorter channels, problems like the junction punchthrough, the leakage, and the contact resistance, cause the reduction in the yield and reliability of the semiconductor manufacturing processes.
The self-aligned silicidation technology is a vital application to improve the operation speed of the ULSI/VLSI MOS devices in manufacturing the sub-micron feature size semiconductor devices. Unfortunately, there exists some trade-off in employing the technologies like self-aligned silicide. In general, the self-aligned silicidation process results a high junction leakage coming from the metal penetration. The metal penetration into the silicon substrate spikes the junction and/or the residual metal to cause the leakage problem. The silicide across the LDD spacer, which is not totally removed after the salicidation, causes the bridge between the adjacent devices like the gate and the source/drain regions. The detailed negative effects of the self-aligned silicidation technology on sub- micrometer devices are illustrated in the article of C. Y. Lu et al. (“Process Limitation and Device Design Tradeoffs of Self-Aligned TiSi2 Junction Formation in Submicrometer CMOS Devices”, in IEEE Trans. Electron Devices, vol. ED-38, No. 2, 1991) The device design tradeoffs for a shallow junction with a salicide structure is proposed. Process limitations of both junction formation schemes for sub-micrometer application and future scaling down are also established in the work.
In present fabrication process, the self-aligned silicide (SALICIDE) technology is widely use to increase the packing density of ULSI circuits and to reduce the interconnect resistance for high speed operation. One of the articles relates to the self-aligned silicide (SALICIDE) technology is the work of K. Fujii et al, titled “A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM” (IEEE, IEDM 96-451, 1996). The above article found that Ti-5% W salicide has high-thermal stability up to 800° C. as well as sheet resistance for 0.18 &mgr;m devices.
As for “short channel effect”, it could be improved by using the extended ultra-shallow source/drain junction. One of the articles relates to the problems is proposed by A. Hori et al. in their work titled “A 0.05 &mgr;m-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5 Kev Ion Implantation and Rapid Thermal Annealing” (IEEE, IEDM 94-485, 1994). A deep submicron PMOSFET has been fabricated together with a NMOSFET. In the proposed process, ultra shallow source/drain junctions were developed on the basis of 5 KeV ion implantation technology and rapid thermal annealing. The short channel effect was successfully suppressed and the delay time per stage of unloaded CMOS inverter is improved at the supply voltage of 1.5V.
SUMMARY OF THE INVENTION
The proposed method in the present invention forms metal oxide semiconductor field effect transistors (MOSFETs) with a recessed self-aligned silicide contact and extended source/drain junctions. The application of self-aligned metal silicide source drain contact, in combination with the metal silicide gate contact, raises the operation speed of the transistors. The structure of the extended ultra-shallow source/drain junctions improves the short channel effects in the conventional devices. The packing density of transistors in integrated circuit can be raised significantly with improved structure formed with the method of the present invention.
The method for fabricating metal oxide semiconductor field effect transistors (MOSFETs) includes steps as follows. At first, isolation regions are formed on a semiconductor substrate and a gate insulating layer is formed on the substrate. A first conductive layer is then formed on the gate insulating layer and a first dielectric layer is formed on the first conductive layer. A removing process is performed to remove portions of the gate insulating layer, the first conductive layer and the first dielectric layer to define a gate structure. A layer formation step is carried out to form a thermal oxide layer on the substrate and on sidewalls of the first conductive layer. Sidewall spacers are then formed on sidewalls of the gate structure. A removing step is carried out to remove portions of the thermal oxide layer uncovered by the sidewall spacers. Another removing step is performed to remove portions of a substrate surface to form recessed regions on the substrate in regions uncovered by the gate structure and the sidewall spacers, preferably by directly etching a substrate material.
Next, the first dielectric layer is removed and a first metal layer is formed on the substrate. A source/drain/gate implantation is performed to the substrate. A thermal process is carried out to convert portions of the first metal layer into a metal silicide layer, which was located over the recessed regions and over the first conductive layer. A removing step then removes unreacted portions of the first metal layer and another step removes the sidewall spacers. Finally, an ion implantation is performed to form the extended source and drain junctions in the substrate under a region covered by the thermal oxide layer.
In addition to the aforementioned process of forming MOS transistors, several subsequent steps are typically performed to form interconnections. Firstly, a second dielectric layer is formed on the substrate and an annealing process is performed to the substrate. Portions of the second dielectric layer are removed to form contact holes. A second metal layer is then formed within the contact holes and on the second dielectric layer. Finally, portions of the se
Acer Semiconductor Manufacturing Corp.
Berezny Neal
Booth Richard
Powell Goldstein Frazer & Murphy LLP
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