Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-23
2003-11-18
Chen, Jack S J (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S289000, C438S299000, C438S586000, C438S589000, C438S597000, C438S618000
Reexamination Certificate
active
06649479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and in particular to a structure of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, a fabrication method thereof, and a structure of a memory cell implemented with the MOSFET device.
2. Description of the Background Art
Recently, as the degree of circuit integration of a semiconductor device has increased, the distance between the source and drain of a MOSFET device has decreased. When the distance between the source and drain decreases below a critical value, the sum of the depletion region of the source and the depletion region of the drain becomes the same as the distance between the source and drain which causes a punch through phenomenon. When the above-described punch through phenomenon occurs, the depletion regions of the source and drain contact each other so that it is impossible to control the current flowing in the MOSFET device.
Since the width of the depletion region is in inverse proportion to the concentration of the dopants, as the concentration of the dopants is increased, the width of the depletion region is decreased. Therefore, in order to overcome the above-described punch through problems, a punch through stopper has been ion-implanted to increase the concentration of dopants in the region in which a channel is formed between the source and the drain.
FIG. 1
is a plan view illustrating a conventional MOSFET device. As shown therein, an active region A and an isolation region B are defined. A first gate
14
a
traverses the active region A, and a second gate
14
b
is formed in the isolation region B. The first gate
14
a
and the second gate
14
b
are integrally connected. First contacts
19
are formed in the active region A at both sides of the first gate
14
a
. A second contact
21
is formed at the second gate
14
b
in the isolation region B.
FIG. 2A
is a cross-sectional view taken along line F-F′ of FIG.
1
. As shown therein, a field insulation layer
3
is formed in an upper portion of a p-type semiconductor substrate
1
, and the region of the semiconductor substrate
1
is divided into an active region A and isolation regions B. A gate insulation film
5
a
, a polycrystal silicon film
7
a
, a silicide film
9
a
, and a capping insulation film
12
a
are sequentially formed on an upper surface of the active region A to form a first gate
14
a
. The capping insulation film
12
a
is formed in a multiple tier structure in which a nitride film is formed on an upper surface of an oxide film. Side wall spacers
15
are formed on both the lateral surfaces of the first gate. A source/drain region
17
is formed in such as manner that a donor is implanted into an upper portion of the p-type semiconductor substrate
1
between the first gate
14
a
and the field insulation layer
3
. The source/drain region
17
is formed of a N+ region
17
a
having a higher doping concentration and a N− region
17
b
having a lower doping concentration. A first contact
19
formed of a conductive material is formed on an upper surface of the source/drain region
17
.
FIG. 2B
is a cross-sectional view taken along line C-C′ of FIG.
1
. As shown therein, a second contact
21
formed of a conductive material is formed on an upper surface of the silicide film
9
b
which is exposed by patterning the capping insulation film
12
b
of the second gate
14
b
formed on the field insulation layer
3
which forms the insulation region B.
The conventional MOSFET device fabrication method will be explained with reference to
FIGS. 3A through 3F
.
As shown in
FIG. 3A
, a trench
2
is formed in the semiconductor substrate
1
, and a field insulation layer
3
is filled into the trench
2
. This divides the semiconductor substrate into an active region A and isolation regions B. A buffer oxide film
25
is formed on an upper surface of the p-type semiconductor substrate
1
. Acceptors such as boron ions, which act as a punch through stopper, are implanted into an upper portion of the active region A of the semiconductor substrate
1
. The buffer oxide film
25
is removed.
Next, as shown in
FIG. 3B
, a gate insulation film
5
a
, a polycrystal silicon film
7
a
, and a silicide film
9
a
are sequentially formed on an upper surface of the semiconductor substrate
1
. Thereafter, an oxide film and a nitride film are sequentially formed on an upper surface of the silicide film
9
a
to form the capping insulation film
12
a.
As shown in
FIG. 3C
, the capping insulation film
12
a
, the silicide film
9
a
, and the polycrystal silicon film
7
a
, which are formed on the semiconductor substrate
1
, are sequentially patterned to form a first gate
14
a
. Donors such as phosphorus ions are implanted into the active region A of the semiconductor substrate
1
using the first gate
14
a
as a mask to form a N− region
17
a.
As shown in
FIG. 3D
, a nitride film is formed on the entire surfaces of the semiconductor substrate
1
including the first gate, and a side wall spacer
15
is formed on a lateral surface of the first gate
14
a
by performing an anisotropical etching operation without using a mask. Donors such as arsenic ions are implanted into the active region A of the semiconductor substrate using the first gate
14
a
and the side wall spacer
15
as a mask. Thereafter, a source/drain region
17
having a LDD (Low Doped Drain) structure of a N+ region
17
b
having a higher doping concentration and a N− region
17
a
having a lower doping concentration are formed based on an annealing operation.
Next, as shown in
FIG. 3E
, the gate insulation film
5
a
is patterned so that a certain region of the upper surface of the source/drain region
17
is exposed. A first contact
19
formed of a conductive material is formed on an upper surface of the exposed source/drain region
17
.
As shown in
FIG. 3F
, a capping insulation film
12
b
of the second gate
14
b
formed on the field insulation layer
3
is patterned, and a certain region of the silicide film
9
b
is exposed. A second contact
21
is formed on an upper surface of the exposed silicide film
9
b
. The second gate
14
b
and the first gate
14
a
are concurrently formed during the same process. In the conventional art, in order to prevent a punch through phenomenon, a punch through stopper is provided in the region in which the channel is formed. However, there is a certain limit for increasing the concentration of a punch through stopper at a region in which a channel is formed. Furthermore, since the source and drain are formed at the same depth, as the density of a device is increased, the margin of the device required for preventing the punch through phenomenon is decreased. Therefore, it is difficult to increase the density, i.e., the degree of integration, of a device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a MOSFET device structure, a fabrication method thereof, and a memory cell which are capable of preventing a punch through phenomenon and which obtain a certain margin of a device which is required for enhancing the degree of integration of the device.
To achieve the above object, there is provided a MOSFET device comprising a semiconductor substrate having an active region, the active region including a first substrate surface at a first level of the substrate, a second substrate surface at a second level of the substrate, the second level being lower than the first level, and a third substrate surface extending from the second substrate surface to the first substrate surface, a first gate formed over the third substrate surface, source/drain regions formed in the first substrate surface and the second substrate surface laterally separated from the first gate, and first conductive contacts formed on the source/drain regions.
In another aspect, the present invention contemplates a method for fabricating a MOSFET device, comprising the steps of provid
Park Seong-Jo
Sung Yang-Soo
Chen Jack S J
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
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