Method for fabricating MOS transistors

Details Method for fabricating MOS transistors Method for fabricating MOS transistors

1999-06-25

2002-10-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S585000, C438S592000, C438S595000

Reexamination Certificate

active

06458641

ABSTRACT:

RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P10 180056 filed Jun. 26, 1998, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating MOS transistors, in particular to a method for fabricating MOS transistors having both a p-type gate electrode of a p-type MOS transistor (PMOS) and a silicon nitride film on a substrate, in which boron (B) in the p-type gate electrode is effectively prevented from diffusing away and from punching through the adjacent gate oxide film.
2. Description of the Related Art
Complementary MOS transistor (CMOS) circuits having both an N-type MOS transistor (NMOS) and a p-type MOS transistor (PMOS) on one and the same substrate have the advantages of reduced power consumption and quick operation as fine patterning to increase the degree of integration in fabricating them is easy, and they have many applications, for example, for memory units and logical units and for other various LSI devices.
Various films of n
+
-type polysilicon films as well as their polycide films or polymetal films as combined with high-melting point metal silicide films or high-melting-point metal films have heretofore been used as the materials for constituting the gate electrode in PMOS for CMOS, like those for the gate electrode in NMOS. The reason is because n
+
-type polysilicon films are well durable in high-temperature processes. In addition, for its channel profile, since the gate electrode of the film of that type has an embedded structure, it enjoys a high bulk mobility and therefore has the advantage of quick operation.
However, in such embedded channel-type MOS transistors, the tip of the depletion layer extending from the source/drain region is too near to another one adjacent thereto in the deep part of the substrate, as being influenced by the gate electric field, thereby often causing punch-through. This means the difficulty in controlling the short channel effect in coming deep sub-micron generation devices in the art. Therefore, it is necessary to change the embedded channel structure to a surface channel structure.
In order to attain the surface channel profile, the gate electrode in PMOS shall be made of a p
+
-type polysilicon film.
Another reason why the p
+
-type polysilicon film is desired for the gate electrode material in PMOS is as follows:
In conventional CMOS circuits where the gate electrodes in NMOS and PMOS are all made of an n
+
-type polysilicon film, the work function differs between NMOS and PMOS and the threshold voltage V
th
in them shall be asymmetric to each other owing to that difference. Therefore, boron ions are implanted in a shallow site in the PMOS channel region so as to make the threshold voltage V
th
in the two transistors NMOS and PMOS nearly equal to each other (generally, at most 1 V). However, the ion implantation for threshold voltage control increases the dopant concentration in the surface of the substrate, whereby the carrier mobility near the surface of the substrate is reduced. The reduction in the carrier mobility is contradictory to quick operation of transistors. Therefore, in coming transistor devices, reducing the channel dopant concentration is indispensable.
However, using a p
+
-type polysilicon film having a large work function in forming the gate electrode in PMOS enables symmetrical threshold voltage V
th
in NMOS and PMOS without increasing the channel dopant concentration. This leads to symmetrical input-output characteristics of transistors having a basic gate structure of CMOS inverters, and even to the improvement in the symmetrical signal transmission characteristics of such transistors.
The CMOS structure in which the gate electrode in PMOS has a p-type conductivity and that in NMOS has an n-type conductivity is referred to as a dual gate CMOS.
In an ordinary process of fabricating CMOS circuits, in general, the gate electrode in NMOS and that in PMOS are all made through patterning of a polysilicon film common thereto. In the process, therefore, different dopant ions are separately implanted in the regions to be the gate electrodes for the two, NMOS and PMOS, via masks, thereby making the gate electrodes for the two have different types of conductivity. Briefly, arsenic (As) ions or phosphorus (P) ions are implanted in the region to be the n
+
-type gate electrode, while boron (B) ions are in the region to be the p
+
-type electrode.
However, the boron implantation is problematic in that the boron introduced into the silicon film often diffuses away when the substrate is exposed to high temperatures in subsequent steps. In that condition, the boron thus having diffused from the silicon film is taken into the gate oxide film or, as the case may be, it punches through the gate oxide film to reach the substrate (Si). The boron diffusion will occur in various scenes in the subsequent steps of, for example, activated annealing of source/drain regions, self-aligned silicification (process for SALICIDE, Self-ALIgned siliCIDE), reflowing of interlayer insulating films, etc., and it causes the increase in the threshold voltage, V
th
, in PMOS, the increase in the sub-threshold swing, and even the reduction in the reliability of gate insulating films.
In addition, it is known that the boron diffusion is accelerated by a silicon nitride film, if formed, around the boron-implanted silicon film.
In one experiment, various MOS capacitors were fabricated and subjected to different types of heat treatment to discuss the problem with them. Precisely, different types of MOS capacitors were fabricated, comprising a gate electrode of a p-type polysilicon film as layered on an n-type silicon (Si) substrate via a gate oxide film having a varying thickness. In some of those, the gate electrode was coated with a silicon nitride film having a thickness of 80 nm via a thin silicon oxide film therebetween. These MOS capacitors were subjected to different types of heat treatment, and their flat band voltage depending on the thickness of the gate oxide film in them was checked.
FIG. 1
shows the gate oxide film thickness dependence of the flat band voltage of the tested MOS capacitors. In this, the vertical axis indicates the flat band voltage(V); and the horizontal axis indicates the thickness (nm) of the gate oxide film.
The p-type gate electrode in those MOS capacitors tested contained boron, and its boron concentration was at least 1×10
20
/cm
3
.
The silicon nitride film was formed through reduced CVD at 760° C., for which was used a mixed gas of dichlorosilane (SiCl
2
H
2
) and ammonia (NH
3
), and its thickness was 80 nm.
Three types of heat treatment, rapid thermal annealing (RTA) at 1000° C. for 10 seconds, furnace annealing in N
2
at 800° C. for 60 minutes, and furnace annealing in N
2
at 760° C. for 135 minutes, were applied to the samples singly or as combined.
Of those heat treatment conditions, the furnace annealing in N
2
at 760° C. for 135 minutes corresponds to the condition for reduced pressure CVD to form a silicon nitride (SiN) film having a thickness of about 80 nm.
During every heat treatment, the surface of the substrate of each sample was entirely covered with a thin capping oxide film so as to protect the boron in the gate electrode from being released away in the ambient vapor phase.
In
FIG. 1
, the graph I indicates the flat band voltage change in the MOS capacitors not coated with a silicon nitride film, for which the capacitors were subjected to RTA at 1000° C. for 10 seconds.
The graph II indicates the flat band voltage change in the MOS capacitors not coated with a silicon nitride film, for which the capacitors were subjected to cycle heat treatment of furnace annealing in N
2
at 760° C. for 135 minutes→furnace annealing in N
2
at 800° C. for 60 minutes→RTA at 1000° C. for 10 seconds.
The graph III indicates the flat band voltage change in the silicon

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