Method for fabricating MOS transistor having dual gate

Details Method for fabricating MOS transistor having dual gate Method for fabricating MOS transistor having dual gate

2000-01-11

2001-12-04

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C438S232000, C438S218000

Reexamination Certificate

active

06326252

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a MOS transistor.
2. Background of the Related Art
FIGS. 1
a
to
1
h
illustrate cross sectional views showing the steps of a related art method for fabricating a MOS transistor having dual gates.
FIG. 2
shows a related art ion injection state.
As shown in
FIG. 1
a,
P type impurity ions and N type impurity ions are respectively injected into isolated regions of a semiconductor substrate
1
to form a P type well
2
and an N type well
3
. As shown in
FIG. 1
b,
a gate oxide film
4
is formed on an active region and a polysilicon layer
5
is deposited on the gate oxide film
4
. The polysilicon layer
5
is deposited at approx. 610° C. using SiH
4
gas, for the purpose of forming small grain sizes. As shown in
FIG. 1
c,
the polysilicon layer
5
and the gate oxide film
4
are selectively removed, to form a gate electrode
5
a
and a gate oxide film portion
4
a
on each of the P type well
2
and the N type well
3
.
As shown in
FIG. 1
d,
a first photoresist film
6
is formed on the substrate
1
such that it covers the N type well
3
, but not the P type well
2
. Then, N type arsenic (As) impurity ions are lightly injected into the exposed surface of the P type well
2
. As shown in
FIG. 1
e,
the first photoresist film
6
is removed. Next, a second photoresist film
7
is formed on the substrate
1
such that it covers the P type well
2
, but not the N type well
3
. Then, P type boron (B
+
) impurity ions are lightly injected into the exposed surface of the N type well
3
.
As shown in
FIG. 1
f,
the second photoresist film
7
is removed, and an oxide film is deposited by chemical vapor deposition (CVD) on the entire upper surface. The oxide film is subjected to anisotropic etching to form oxide film sidewalls
8
at the sides of each gate electrode
5
a.
Then, nitrogen ions are injected into the gate oxide film
4
a
and the oxide film sidewalls
8
. The nitrogen ions are injected for preventing penetration of boron (B
+
) from the P type gate electrode
5
a
during a heat treatment in a later process.
As shown in
FIG. 1
g,
a third photoresist film
9
is formed on the entire surface of the transistor, except for the P type well
2
. Then, N type impurity ions of arsenic (As
+
) are heavily injected into both a surface of the exposed P type well
2
and to the N type gate electrode
5
a.
Next, as shown in
FIG. 1
h,
the third photoresist film
9
is removed, and a fourth photoresist film
10
is formed on the entire surface except for the N type well region
3
. P type impurity ions of boron (B
+
) are heavily injected into both a surface of the exposed N type well
3
and into the P type gate electrode
5
a.
Then, the fourth photoresist film
10
is removed, and a heat treatment is conducted at approx. 1000° C. in a nitrogen ambient, to diffuse impurity ions.
The related art method for fabricating an MOS transistor having dual gates has at least the following problems, as shown, for example, in
FIG. 2
, which illustrates a state of a related art ion injection into a gate electrode.
First, amorphous or columnar silicon is deposited for forming a dual gate electrode. However, a heat treatment in an amorphous state causes depletion in an NMOS region, and the heat treatment of the columnar structure alters device characteristics due to channeling during ion injection. A diffusion speed of the boron in a NMOS region is significantly faster than a diffusion speed of the arsenic in a NMOS region. If the heat treatment is completed long after the injection of arsenic and boron, the boron passes the gate oxide film
4
a
and invades the substrate
1
, which results in channeling. If the time period of the heat treatment is short, the slow diffusion speed of the arsenic in the NMOS region causes depletion of the NMOS region. Moreover, the columnar polysilicon has a preferred orientation in a plane (
110
) that is very susceptible to channeling during ion injection, while polysilicon, other than amorphous or columnar, has a preferred orientation in a plane (
111
). In this environment, boron with a smaller ion radius causes channeling which enhances boron penetration during heat treatment and changes characteristics of the device.
Second, as discussed above, nitrogen ions are injected into the gate insulating film
4
a
before impurity ions are heavily injected into the P type gate electrode
5
a.
Although penetration of boron injected into the P type gate electrode into regions below the gate insulating film can be prevented during the heat treatment, reduction of an impurity concentration in the N type gate electrode cannot be prevented in the related art approach because arsenic ions injected into the N type gate electrode are outwardly diffused. Accordingly, device characteristics of the NMOS region deteriorate in the related art method.
SUMMARY OF THE INVENTION
An object of the present invention is to substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to suppress dopant depletion in a NMOS region.
Still another object of the present invention is to suppress boron penetration into a PMOS region.
Yet another object of the present invention is to minimize outward diffusion of impurities injected into a gate electrode.
Yet still another object of the present invention is to reduce a sheet resistivity of the gate electrode.
A further object of the present invention is to minimize impurity channeling and diffusion.
The objects of the present invention can be achieved in a whole, or in part, by fabricating a MOS transistor having dual gates. A first conduction type well and a second conduction type well are formed in a semiconductor substrate having an isolation region and an active region formed therein. A gate oxide film on an entire surface of the substrate is formed, and polysilicon layer is deposited on the gate oxide film, preferably at 660° C.~700° C. and 10~300 Torr. The polysilicon layer and the gate oxide film are selectively removed to form a gate electrode on each of the wells. Impurity ions having a conduction type opposite to a corresponding well is injected into an exposed surface of the respective well, to form lightly doped impurity regions. Insulating film sidewalls are formed at sides of each of the gates.
Next, first conduction type impurity ions, having a conduction type opposite the conduction type of the first conduction type well, are heavily injected into a surface of the exposed first conduction type well and into the gate electrode formed on the first conduction type well. Second conduction type impurity ions, having a conduction type opposite the conduction type of the first conduction type well, are heavily injected into a surface of the exposed second conduction type well and into the gate electrode formed on the second conduction type well. Then a first heat treatment is conducted in an oxygen ambient, and a second heat treatment is conducted in a nitrogen ambient, to diffuse impurities.
The objects of the present invention can also be achieved in a whole, or in part, by fabricating a transistor having dual gates. A first heat treatment of first and second doped impurity regions of a semiconductor device is conducted in an oxygen ambient. A second heat treatment of the first and second doped impurity regions of the semiconductor device is conducted in a nitrogen ambient to reduce a sheet resistivity of the dual gates.
In addition, the objects of the present invention can be achieved in a whole, or in part, by a method of fabricating a transistor. A gate oxide film is formed, at about 660° C. to about 700° C., and at a pressure of about 10 to 300 Torr, over first and second conduction type wells of a semiconductor substrate having corresponding first and second conduction types. A polysilicon layer is then deposited over the g

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