Method for fabricating MOS devices with a salicided gate and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S301000, C438S303000, C438S592000, C438S199000, C257SE21438

Reexamination Certificate

active

07842578

ABSTRACT:
A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.

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patent: 6506670 (2003-01-01), Schoenborn
patent: 2003/0178665 (2003-09-01), Takenaka
patent: 2008/0272420 (2008-11-01), Lee
patent: 1147691 (1997-04-01), None
patent: 1435875 (2003-08-01), None

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