Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-30
2004-11-23
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S250000, C438S393000, C438S396000
Reexamination Certificate
active
06821839
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating an MIM capacitor, and more particularly to a method for improving leakage current property of an MIM capacitor.
2. Description of the Prior Art
Currently, analog capacitors are being converted from the PIP (Poly-Insulator-Poly) structure to the MIM (Metal-Insulator-Metal) structure. This is because a capacitor for use in an analog circuit with an RF band requires a high quality factor value. In order to achieve this, it is necessary to use a metallic electrode material with little depletion and low resistance for the electrode.
FIG. 1
shows a structure of an MIM capacitor. Similar to a conventional capacitor, the MIM capacitor has a structure including a lower electrode
11
, an upper electrode
13
and a dielectric layer
12
interposed therebetween. In this structure, TiN is used for the lower electrode
11
and a material with a high dielectric constant, such as Ta
2
O
5
, is used for the dielectric layer
12
.
More specifically, the lower electrode
11
includes a metallic electrode layer, such as a copper layer or an aluminum layer, along with a metallic barrier layer, such as a TiN, TaN, Ta, or Ti layer (preferably a TiN layer), formed on the surface of the electrode metallic layer.
In
FIG. 1
, a semiconductor substrate
1
is indicated with
11
, a base layer with
10
, a MIM capacitor with
14
, an insulator layer for interposing between the layers with
15
, and metallic wires with
16
and
17
.
However, the conventional MIM capacitor has a few problems in that its polarity is poor and that its leakage current property is extremely poor. This is because the TiN layer used as the material for the lower electrode has poor surface roughness in respect of its columnar structure, as shown in FIG.
1
. Also, this is because the lower electrode is oxidized during a post treatment. The post treatment, such as an O
2
-plasma treatment or an O
3
-annealing, should be performed after deposition in order to ensure the leakage current property of the dielectric material, such as Ta
2
O
5
.
In other words, when a positive (+) bias is applied to the upper electrode, a concentration of electric field occurs due to the roughness of the surface of the lower electrode. Accordingly, the leakage current property deteriorates in comparison to a case in which a negative (−) bias is applied to the upper electrode.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming a MTM capacitor capable of preventing inferiority in polarity and the ability to prevent leakage current due to poor surface roughness of a lower electrode and surface oxidization of the lower electrode during an O
2
treatment.
In order to accomplish this object, there is provided a method for forming a MIM capacitor, the method comprising steps of: providing a semiconductor substrate formed with a base layer including a metallic pattern; depositing a first metallic layer used for a lower electrode on the base layer; depositing a first middle layer on the first metallic layer in order to improve the surface roughness of the first metallic layer and prevent an oxidization thereof; depositing a dielectric layer with a high dielectric constant on the first middle layer; depositing a second middle layer on the dielectric layer in order to increase band gap energy; depositing a second metallic layer to be used for the upper electrode on the second middle layer; and patterning the first metallic layer to thus complete formation of the lower electrode.
According to an aspect of the present invention, the first and the second middle layers are one selected from a group including a nitride layer, a silicon oxide layer and an aluminum oxide layer. Preferably, the first and the second middle layers are nitride layers.
According to another aspect of the present invention, a nitride layer is deposited with a thickness of between 10 and 200 Å by a PECVD process performed at a temperature of between 300 and 500 degrees Celsius.
REFERENCES:
patent: 4613546 (1986-09-01), Kuwata et al.
patent: 6341056 (2002-01-01), Allman et al.
patent: 6451667 (2002-09-01), Ning
patent: 6504202 (2003-01-01), Allman et al.
patent: 6566186 (2003-05-01), Allman et al.
patent: 2003/0068858 (2003-04-01), Allman et al.
patent: 2003/0098484 (2003-05-01), Kim
Fourson George
García Joannie A.
Hynix / Semiconductor Inc.
Ladas & Parry LLP
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