Method for fabricating metal oxide semiconductor field...

Details Method for fabricating metal oxide semiconductor field... Method for fabricating metal oxide semiconductor field...

1999-09-21

2001-12-04

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S300000, C438S589000, C438S606000, C438S635000

Reexamination Certificate

active

06326317

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) and more particularly to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a gallium arsenide (GaAs) substrate.
BACKGROUND OF THE INVENTION
For several ten years, the field effect transistor (FET) has been significantly developed in the application of semiconductor device. Due to its low-power dissipation and highly integrated technique, it plays the most important role in the field of very-large-scale integration (VLSI), particularly in ultra-large-scale integration (ULSI). There are many kinds of FET design, in which the main differences are in the gate and channel structures. In the fabrication of an integrated circuit using silicon as a material, a metal oxide semiconductor FET (MOSFET) has the properties of high yield rate and excellent reliability in addition to the above-described advantages of FET. Therefore, MOSFET has become the commonly used device in recent years. Certainly, there are some other designs for FET, such as a metal-insulator-semiconductor (MOSFET), an insulator-gate FET (IGFET), a junction-gate FET (JFET) using reversely biased p-n junction as a gate, a metal-semiconductor FET (MOSFET) using the metal-semiconductor schottky contact as a gate, and a modulation-doped FET (MOSFET).
In the fabrication of an integrated circuit using a GaAs material, although the electron mobility of GaAs is several times higher than that of silicon, the former is not so popular as the latter when used in the semiconductor industry. Except for its relatively expensive cost, the reason is that GaAs is unstable at a temperature greater than 650° C. so that a high-quality oxide layer can not be fabricated in the high-temperature tube. The oxide layer with bad reliability and low interface density will bring about a difficulty in the fabrication of enhancement-mode MOS and limit the design and operation of many other FET structures. Therefore, it is desirable to overcome the problem encountered by the application of GaAs material.
In our previous studies (please see Hwei-Heng Wang et al., Japanese J. of Applied Physics, Pt. 2 (Letters) Vol. 37, No. 1 AB, pp. L-67-L70, 1998), we proposed a method for selectively forming an oxide layer on a portion uncovered by the photoresist or noble netal layer near the room temperature (40~70° C.). Thus, how to combine the above-described processes for manufacturing the field effect transistors with this method and use GaAs as a substrate of metal oxide semiconductor FET (MOSFET) is the developing purpose of the invention.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a gallium arsenide (GaAs) substrate.
In the first preferred embodiment of the present invention, the method includes the steps of (a) providing a substrate; (b) forming an epitaxial layer on the substrate; (c) defining and forming a drain and a source on a portion of the epitaxial layer; (d) forming a recess in another portion of the epitaxial layer; (e) forming an oxide layer on a surface of the recess by relatively low-temperature oxidation; and (f) forming a gate on a portion of the oxide layer between the drain and source.
Preferably, the substrate is a semi-insulating GaAs substrate.
The epitaxial layer includes a buffer layer, a moderately doped layer, and a heavily doped layer. The buffer layer is an undoped layer and has a thickness of about 5000 Å. The moderately doped layer has a thickness ranging from 2000 Å to 3000 Å, a concentration of 10
16
~10
17
cm
31 3
, and serves as a channel. The heavily doped layer has a thickness of 1000 Å, a concentration greater than 10
18
cm
−3
, and serves as an ohmic contact for the source and drain.
After the step (b), the method further includes a step (b1) of immersing the wafer in 2-propanol, acetone, and methanol in sequence and cleaning the wafer by an ultrasonic oscillator. Thereafter, a lithographic process is performed to etch the epitaxial layer for giving a mesa isolation, in which the mesa deepens to a place lower than the buffer layer to isolate all formed devices on the wafer, and a height of the mesa ranges from 6000 Å to 8000 Å. The mesa isolation is achieved by using an etching solution containing HF, H
2
O
2
, and H
2
O (HF: H
2
O
2
: H
2
O=1:2:25 by volume) for giving rounded edges to the mesa.
Certainly, the step (c) further includes steps of: (c1) coating a photoresist on the epitaxial layer; (c2) performing a lithographic process to pattern the photoresist for defining and forming the drain and source on the portion of the epitaxial layer; (c3) coating an alloy film on the drain and source; (c4) using a lift-off procedure to leave a drain/source metal in place; and (c5) executing an annealing process to accomplish a metallization process of the drain and source. In the step (c3), the alloy film is deposited by e-beam evaporation using Au/Ge/Ni or Au/Be. In the step (c5), the annealing process is performed at 450~600° C. for 10~25 seconds.
In the step (d), the epitaxial layer is partially etched by using an etching solution containing NH
3
, H
2
O
2
, and H
2
O (NH
3
: H
2
O
2
: H
2
O=3:1:50 by volume) and using the drain/source metal as a mask to form the recess in the another portion of the epitaxial layer.
In the step (e), a formed thickness of the oxide layer is controlled by using 1.15M nitric acid solution containing 0.36 mole of Ga ion whose initial pH value is adjusted to 4.3 by 2.5% ammonium hydroxide hydroxide (NH
4
OH) solution. During the formation of the oxide layer, an ammonium hydroxide solution, prepared from diluting 28% ammonium hydroxide solution with de-ionized water to 300 folds, is added therein for adjusting the pH value within a range between 4.0 and 5.0 to control the growth rate and refractive index of the formed oxide layer.
The gate is formed by steps of coating a photoresist on the fabricated wafer, performing a lithographic process to pattern the photoresist for defining a gate region on the portion of the oxide layer, coating a conducting layer with a relatively high conductivity on the defined region for the gate, and using a lift-off procedure to form the gate on the portion of the oxide layer. Preferably, the conducting layer can be made of gold, aluminum, or polysilicon.
In the second preferred embodiment of the present invention, the step (e) further includes a step (e1) of performing a synchronic sulfurated passivation process by adding a processed (NH
4
)
2
S solution, prepared from adding sulfur powder to (NH
4
)
2
S solution, stirring, and filtering out the undissolved sulfur powder, to a system solution for forming the oxide layer at any time during the formation of the oxide layer.
In the third preferred embodiment of the present invention, after the step (e1), the method further includes a step (e2) of performing a rapid thermal annealing (RTA) process, wherein the wafer is heat-treated and irradiated for several to several ten seconds. Certainly, after performing the rapid thermal annealing process, the method further includes a step of immersing the wafer in 2-propanol, acetone, and methanol in sequence and cleaning the fabricated wafer by an ultrasonic oscillator to remove an impurity deposited on the fabricated wafer during the rapid thermal annealing process.
In the fourth preferred embodiment of the present invention, the method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) includes the steps of: (a) providing a substrate; (b) forming an epitaxial layer on the substrate; (c) forming a recess in a first portion of the epitaxial layer; (d) forming an oxide layer over a surface of the recess and a second portion of the epitaxial layer by relatively low-temperature oxidation; (e) defining and forming a drain and a source on a third portion of the epitaxial layer; and (f) forming a gate on

Affiliated with

Also associated with

Rating

Method for fabricating metal oxide semiconductor field... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating metal oxide semiconductor field..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating metal oxide semiconductor field... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2576853