Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-03
2001-02-20
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S307000, C438S306000, C438S291000, C438S290000
Reexamination Certificate
active
06190981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a semiconductor fabricating method, and more particularly to a fabricating method for a teal oxide semiconductor (MOS).
2. Description of the Related Art
As integrated circuits become more complicated and their function becomes more powerful, the required density of transistors in an integrated circuit increases correspondingly. The high density of these complex integrated circuits cannot be easily achieved by simply decreasing a layout according to device proportions of the integrated circuits. The device size must be decreased by a design rule and with consideration for possible change in the physical characteristics of the device. For example, channel length of a MOS transistor cannot be reduced infinitely. Reduction size may cause a short channel effect. Once the short channel effect happens, a punchthrough problem is likely to occur. The punchthrough problem occurs due to current leakage when the MOS transistor is switched off. The conventional solution to the punchthrough problem is to increase punchthrough voltage, in a procedure such as a punchthrough stopper implantation or a halo implantation.
FIG.
1
and
FIG. 2
respectively explain the related positions of an anti-punchthrough region and a MOS formed by conventional methods.
In
FIG. 1
, an N-type MOS is taken as an example. In a typical punchthrough stopper implantation, P-type impurities are implanted in the substrate
100
before forming a gate
106
and a source/drain region
120
. A heavily doped anti-punchthrough region
114
is formed in the substrate
100
below the surface-channel region
112
between the source/drain region
120
.
In
FIG. 2
, a tilt-angle halo implantation step is performed after a gate
206
and a source/drain extension
210
a
are formed. P-type impurities are locally implanted in the substrate
200
. An anti-punchthrough region
214
, which is connected to the source/drain extension
210
a
, is formed in the substrate
200
. In contrast with the anti-punchthrough region
114
formed by punchthrough stopper implantation, the anti-punchthrough region
214
formed by halo-implantation, which region connects to the extension region
210
a
, has higher anti-punchthrough ability. Hence, the anti-punchthrough region
214
is more suitable than the anti-punchthrough region
114
for a MOS occupying a small planar area.
A depletion region usually exists at an interface of the interchangeable source/drain region and the substrate due to, for example, a depletion of electron holes for a P-type substrate. This depletion region behaves like a capacitor and contributes a junction capacitance. The junction capacitance is larger if the depletion region is larger. The depletion region is larger if the dopant density is larger or junction contact area is larger. A higher dopant density also needs a higher dopant density in the anti-punchthrough region formed by halo-implantation in order to reduce a short channel effect. However, another depletion region also exists at an interface between the anti-punchthrough region formed by halo-implantation and the source/drain region. Since the anti-punchthrough region carries higher dopant density, it results in a higher junction capacitance. It is natural for an AC circuit that the junction capacitance can reduce an alternative-current (AC) operation speed. In addition, the gate oxide layer also induces an oxide capacitor, which is coupled with the junction capacitor in series. The oxide capacitor increases the junction capacitance and causes a slower AC operation speed.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved method for forming a halo doped region by self-alignment. The improved method includes a formation of the halo doped region below a source/drain extension and between a source/drain region so as to control a short channel effect.
It is another objective of the present invention to provide an improved method for forming a MOS transistor. The improved method includes a formation of an offset spacer on the sidewall of the gate of the MOS transistor so as to reduce a lateral extension length of the source/drain extension. The overlap region between the gate and the source/drain extension is therefore reduced so that a less overlapping capacitance can be obtained. An AC operation speed is further increased.
It is still another objective of the present invention to provide a method for forming a MOS transistor. The MOS transistor comprises an air gap between the gate and an insulating spacer beside the gate. Since the dielectric constant of the air gap is very low, a parasitic capacitance formed between the gate and other conductor adjoining the insulating spacer is decreased.
It is still another objective of the present invention to provide an improved method for forming a MOS transistor. A halo doped region, which has a smaller area than a convention halo doped region, is formed below the source/drain extension so as to reduce the junction capacitance. Thus a margin of the junction can be more easily controlled
The invention achieves the above-identified objects by providing a method of fabrication for a MOS transistor. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.
REFERENCES:
patent: 5736446 (1998-04-01), Wu
patent: 5759901 (1998-06-01), Loh et al.
patent: 5908313 (1999-06-01), Chau et al.
patent: 5914519 (1999-06-01), Chou et al.
patent: 5972762 (1999-10-01), Wu
patent: 5972763 (1999-10-01), Chou et al.
patent: 5994747 (1999-11-01), Wu
patent: 5998284 (1999-12-01), Azuma
patent: 6015746 (2000-01-01), Yeh et al.
patent: 6046472 (2000-04-01), Ahmad et al.
patent: 6049114 (2000-04-01), Maiti et al.
patent: 6064107 (2000-05-01), Yeh et al.
Chou Jih-Wen
Lin Tony
Park James
United Microelectronics Corp.
Wilczewski Mary
LandOfFree
Method for fabricating metal oxide semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating metal oxide semiconductor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating metal oxide semiconductor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2592609