Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-15
2002-03-19
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S393000
Reexamination Certificate
active
06358792
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a metal capacitor, and more particularly to a method for fabricating a metal capacitor in which the lower electrodes are concurrently formed with an interconnect metal.
2. Description of the Prior Art
In conventional VLSI (very large scale integrated) capacitor process, capacitors are of the so-called “double poly” type. That is, the upper and lower electrodes are formed of polysilicon. However, since the polysilicon layers have depletion regions, which induces parasitic capacitance, they cannot meet the requirement of low voltage coefficient of capacitance.
In recent years, the “double poly” type of capacitor has gradually been replaced by a metal capacitor, in which the upper and lower electrodes are formed of metal.
For example, U.S. Pat. No. 5,479,316 discloses a method for making a metal capacitor, in which two metal layers serve as the upper and lower electrodes of the capacitor.
In U.S. Pat. No. 5,086,370, a method for making a metal capacitor having a low voltage coefficient is disclosed. The lower electrode is a polysilicon layer clad with a TiSi
2
thin film, and the upper electrode is a TiN thin film with a polysilicon layer formed thereon. Thus, the depletion region is decreased, and,the capacitor has a low voltage coefficient.
However, in the above-mentioned cases, one process is complicated, and the other process requires additional metal layers to serve as the upper/lower electrodes, wasting space and material.
Refer to
FIGS. 1
a
to
1
f
, which are cross-sectional views illustrating the process flow of fabricating a metal capacitor in an intermetal dielectric layer according to conventional process. Referring to
FIG. 1
a
, a semiconductor substrate
100
including a MOS transistor (not shown) is provided. A plurality of first level metal lines
120
and
121
are formed on the substrate
100
, and a first intermetal dielectric layer
110
is formed on the substrate
100
and the metal lines
120
and
121
. A first resist pattern
140
is formed on the first intermetal dielectric layer
110
. The first intermetal dielectric layer
110
is then patterned by photolithography and etching using the first resist pattern
140
as a mask to form a via hole. Metal is then filled into the via hole to form a first plug
150
, and the first resist layer
140
is removed.
Next, referring to
FIG. 1
b
, a metal layer
160
, an insulating layer
170
, and a metal layer
180
are successively formed on the entire surface of the first intermetal dielectric layer
110
and the first plug
150
. A second resist pattern
190
is formed on the metal layer
180
. The second resist pattern
190
defines a region for forming a metal capacitor in the future, which is called a capacitor region
130
. Then, the metal layer
160
, the insulating layer
170
, and the metal layer
180
are patterned by photolithography and etching using the second resist pattern
190
as a mask to define a metal capacitor
200
which includes a lower electrode
160
′, an insulating layer
170
′, and an upper electrode
180
′ as shown in
FIG. 1
c.
Next, referring to
FIG. 1
d
, a second intermetal dielectric layer
210
is formed on the metal capacitor
200
and the first intermetal dielectric layer
110
.
Next, referring to
FIG. 1
e
, a third resist pattern
220
is formed on the second intermetal dielectric layer
210
. The second intermetal dielectric layer
210
is then patterned by photolithography and etching by using the third resist pattern
220
as a mask to form a via hole in the capacitor region
130
reaching the upper electrode
180
′ and a via hole reaching first level metal line
120
, which are then filled with metal to form a second plug
230
and a third plug
240
.
Finally, referring to
FIG. 1
f
, second level metal lines
250
and
251
are formed on the plugs
230
and
240
respectively for electrical connection.
The conventional method for fabricating a metal capacitor in an intermetal dielectric layer has the following disadvantages:
(1) Two masks are needed to fabricate a metal capacitor. That is to say, one mask is needed when the plug
150
is defined and the other mask is needed when the metal capacitor is patterned. Thus, costs are high.
(2) Since the cross-sectional area of the plug
150
is small, when the plug
150
is defined, etching is very difficult to control, complicating the process.
(3) When the plugs
230
and
240
are concurrently defined, since the etching heights for the two plugs differ a lot, etching is difficult to conduct, complicating the process.
(4) Since the metal layer
160
, the insulating layer
170
, and the metal layer
180
for forming the metal capacitor are formed on the entire surface, production costs are very high.
(5) When the metal layer
160
, the insulating layer
170
, and the metal layer
180
are etched to form the metal capacitor, it is very easy to cause damage on the edge portion of the metal capacitor. Thus, yield is decreased.
SUMMARY OF THE INVENTION
The object of the present invention is to solve the above-mentioned problems and to provide a method for fabricating a metal capacitor, which is simple, has decreased production costs, and increased yield.
To achieve the above-mentioned object, the method for fabricating a metal capacitor according to the present invention includes the following sequential steps. A first level metal layer is formed on a substrate. The first level metal layer is patterned to concurrently form a first metal line and a second metal line, wherein the second metal line defines a metal capacitor region and is used as a lower electrode of the metal capacitor. An insulating layer is formed conformably on the substrate, the first metal line, and the second metal line. A first intermetal dielectric layer is formed on the insulating layer. The first intermetal dielectric layer is subjected to planarization treatment such that the planarization treatment ends up to the insulating layer. A third metal line is formed on the insulating layer in the metal capacitor region such that the third metal line is used as an upper electrode of the metal capacitor.
After the upper electrode is formed, the method for fabricating the metal capacitor according to the present invention can further include the following steps. A second intermetal dielectric layer is formed on the upper electrode, the insulating layer, and the first intermetal dielectric layer. The second intermetal dielectric layer is patterned to form a first via hole reaching the first metal line and a second via hole reaching the upper electrode. Metal is filled into the first and the second via holes to form a first and a second plugs respectively. A second level metal layer is formed on the second intermetal dielectric layer, the first plug, and the second plug. The second level metal layer is patterned to form a fourth metal line on the first plug and a fifth metal line on the second plug.
The main difference between the method of the present invention and the conventional method resides in the fact that, in the present invention, the lower electrode and an interconnect metal line are located at the same level. That is to say, the lower electrode and the interconnect metal line can be in-situ (concurrently) formed. Thus, one mask can be omitted compared with the conventional method, and a step of photolithography and etching can be omitted.
In the present invention, production costs are decreased, process complexity is decreased, yield is enhanced, and the object of minaturizing integrated circuits is achieved.
REFERENCES:
patent: 5086370 (1992-02-01), Yasaitis
patent: 5479316 (1995-12-01), Smrtic et al.
patent: 5607873 (1997-03-01), Chen et al.
patent: 6291307 (2001-09-01), Chu et al.
Hsue Chen-Chiu
Lee Shyh-Dar
Silicon Integrated Systems Corp.
Tsai Jey
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