Method for fabricating merged logic CMOS device

Details Method for fabricating merged logic CMOS device Method for fabricating merged logic CMOS device

2005-09-06

2005-09-06

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000

Reexamination Certificate

active

06939757

ABSTRACT:
A method for fabricating a merged logic device is disclosed which simplifies the process by forming a deep junction of a double diffused drain (DDD) structure by a retrograded well ion implantation process. The method includes forming a high voltage p-type well region on a semiconductor substrate; simultaneously conducting an ion implantation for forming a logic p-type well region on a logic region and a high voltage n-type well region on the high voltage p-type well region; forming a high voltage gate oxide film on the entire surface and conducting a threshold voltage ion implantation process; forming a logic gate oxide film on the logic region and simultaneously forming a logic gate electrode and a high voltage gate electrode; forming a logic DDD region on the logic region and forming spacers on the sides of the gate electrodes; and forming logic source/drain regions, high voltage source/drain regions and a bulk bias control region.

REFERENCES:
patent: 5340756 (1994-08-01), Nagayasu
patent: 5565369 (1996-10-01), Ko
patent: 5702988 (1997-12-01), Liang
patent: 6071775 (2000-06-01), Choi et al.
patent: 6512273 (2003-01-01), Krivokapic et al.

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