Method for fabricating merged dram with logic semiconductor...

Details Method for fabricating merged dram with logic semiconductor... Method for fabricating merged dram with logic semiconductor...

2002-10-21

2004-08-24

Klinger, James (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S258000, C438S279000, C438S286000, C438S926000

Reexamination Certificate

active

06780715

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Application No. P2001-65793 filed on Oct. 24, 2001 under 35 USC § 119, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a method for fabricating an MDL (Merged DRAM with Logic) semiconductor device, in which silicide is formed selectively on a logic region and a memory region for enhancing the device reliability.
2. Discussion of the Related Art
As a device packing density increases, the MDL type device is born in a form where a memory (DRAM) and a logic circuit are merged into one chip as a previous stage of a system on chip product for meeting different demands of consumers. Recently, because the MDL composite chip has advantages of providing a small sized, high speed device with a low EMI (Electro Magnetic Interference) and with a low power consumption, researches on the development of the MDL composite chip with a memory product and a logic product formed on one chip, are active in many fields. However, an MDL fabrication process itself is complicated and difficult because a process for fabricating the memory product and a process for fabricating the logic circuit need to be taken into consideration at the same time.
A related art method for fabricating an MDL semiconductor device will be explained with reference to the attached drawings.
FIGS. 1A-1J
illustrate sectional views showing the steps of a related art process for fabricating an MDL semiconductor device,
FIGS. 2A-2F
illustrate sectional views showing the steps of another related art process for fabricating an MDL semiconductor device, and
FIGS. 3A-3E
illustrate sectional views showing the steps of still another related art process for fabricating an MDL semiconductor device.
In general, in the related art MDL semiconductor device, a logic part is required to have high performance while a memory part is required to have reliability. To satisfy these requirements, a gate oxide film with different thicknesses is applied to each of the logic region and the memory region of the device, and a dual poly structure is employed in a transistor in the logic region. In the logic region, for improving device packing density and performance, salicide structures are employed in a gate surface and active surface. In the memory region, for improving the reliability and refresh characteristics, a diffusion active region is employed.
In order to simplify the fabrication process in the related art MDL semiconductor device, either a polycide gate structure (
FIGS. 2A-2F
) or a salicide gate structure (
FIGS. 3A-3E
) is employed for forming identical gate structures in the memory region and the logic region. Alternatively, taking characteristics of each region into consideration, a polycide structure is employed in the memory region and the polycide region is removed from the logic region to form a gate according to the fabrication steps shown in
FIGS. 1A-1J
.
The steps of a related art process for fabricating the MDL semiconductor device will now be explained in more detail referring to
FIGS. 1A-1J
.
At first, referring to
FIG. 1A
, a device isolation layer
3
is formed in a semiconductor substrate
26
(or a well region (not shown)) having a logic region
1
and a memory region
2
divided by a boundary line B. In this instance, if an NMOS transistor formation region is taken into consideration, doping concentration in the logic region
1
and the memory region
2
may differ. That is, for improving cell refresh characteristics of the memory region
2
, the doping concentration of the memory region
2
may be made relatively low. Then, a first gate oxide film
4
with a first thickness and a first gate forming material layer
5
are formed on the entire surface of the substrate
26
in succession. The first gate forming material layer
5
is formed of undoped polysilicon. Then, a first capping layer
6
of oxide or nitride is formed on the first gate forming material layer
5
for preventing etch damage to the gate layer during the gate etching process.
Referring to
FIG. 1B
, a photoresist layer is formed on the entire surface of the substrate and patterned selectively for forming a first photoresist pattern layer
7
in the logic region
1
and not in the memory region
2
. The exposed first capping layer
6
, first gate forming material layer
5
, and first gate oxide film
4
are etched selectively by using the first photoresist pattern layer
7
as a mask so that no layer remains above the memory region
2
of the substrate
26
. Thereafter, the first photoresist pattern layer
7
is removed.
Referring to
FIG. 1C
, a second gate oxide film
8
with a second thickness thicker than the first thickness of the first gate oxide film
4
, a second gate forming material layer
9
for forming a memory, a tungsten silicide layer
10
and second capping layers
11
and
12
are formed in succession on the entire surface of the resultant structure. In this instance, a polycide structure is used to improve the reliability of the memory and a capacitor forming process to be applied later. The second capping layers
11
and
12
are a stack of an oxide film (
11
) and a nitride film (
12
).
Referring to
FIG. 1D
, photoresist is applied on the entire surface of the resultant structure, and patterned selectively to form a second photoresist pattern layer
13
for patterning a wordline in the memory region
2
. A stack of the layers
8
,
9
,
10
,
11
, and
12
in the memory region
2
is etched selectively by using the second photoresist pattern layer
13
as a mask, to form gates
14
of a DRAM cell. Thereafter, the second photoresist pattern layer
13
is removed.
Referring to
FIG. 1E
, source/drain regions
15
are formed in surfaces of the substrate
26
in the exposed memory region
2
by using the gates
14
as a mask. Then, a sidewall spacer forming layer made of oxide or oxide
itride is formed on the entire resultant structure and etched back to form DRAM sidewall spacers
16
at the sides of each gate
14
of a DRAM cell to form a storage node contact by SAC (Self-Aligned-Contact) in the following process. At the same time, a sidewall spacer is formed at the side of the stack of layers
4
-
6
and
8
-
12
in the logic region
1
. Then, a material such as BPSG (Boron-Phosphorus-Silicate-Glass), PSG (Phosphorus-Silicate-Glass), HDP (High Density Plasma), or SOG (Spin On Glass) is deposited on the entire surface of the resultant structure to form a gap filling material layer
17
filling the gaps in the memory region
2
and the logic region
1
.
Referring to
FIG. 1F
, the gap filling material layer
17
is planarized by CMP (Chemical Mechanical Polishing) to form a DRAM gate gap filling layer
17
a.
Referring to
FIG. 1G
, photoresist is coated on the entire surface of the resultant structure, and patterned to leave the photoresist only in the memory region
2
as a third photoresist pattern layer
18
. Then, material layers
6
,
8
,
9
,
10
,
11
, and
12
for forming a DRAM, which remained in the logic region
1
, are removed by using the third photoresist pattern layer
18
as a mask to expose the first gate forming material layer
5
in the logic region
1
. In this instance, there remains a residual layer
19
at an interface between the logic region
1
and the memory region
2
. Thereafter, the third photoresist pattern layer
18
is removed.
Referring to
FIG. 1H
, photoresist is coated on the entire surface of the resultant structure, and patterned selectively to form a fourth photoresist pattern layer
20
on the first gate forming material layer
5
in the logic region
1
for forming a logic gate. Then, the first gate oxide film
4
and the first gate forming material layer
5
, both in the logic region
1
, are selectively etched by using the fourth photoresist pattern layer
20
as a mask, to form logic gates
21
. The fourth photoresist pattern layer
20
is removed.
Referring to
FIG. 1I
, impurities are l

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