Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-05-09
2004-08-03
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S230000, C438S304000, C438S585000
Reexamination Certificate
active
06770532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for fabricating a gate, and more particularly to a method for fabricating a T-shaped gate.
2. Description of the Related Art
The size of memory units is reduced and integration is increased at the semiconductor fabricating process. In the fabricating process of a gate, a pattern of the gate is developed a mask to a photoresist layer, and then transferred to a hard mask layer. A conducting layer is etched to form a gate using the patterned hard mask layer as a mask. The pattern of the gate in the photoresist layer is narrower when the width of the gate is smaller. Furthermore, the resolution is better when the thickness of the photoresist layer is thinner, but the etch resistance is reduced.
FIGS. 1
a
to
1
c
are cross-sections of the conventional method for forming a gate.
In
FIG. 1
a
, a semiconductor substrate
101
is provided, and a gate dielectric layer
102
, a conducting layer
103
, a hard mask layer
104
, and a patterned photoresist layer
105
are sequentially formed thereon.
In
FIG. 1
b
, the hard mask layer
104
, the conducting layer
103
, and the dielectric layer
102
are sequentially etched to form a gate
103
a
and a gate dielectric layer
102
a
using the patterned photoresist layer
105
as a mask.
In
FIG. 1
c
, the patterned photoresist layer
105
and the hard mask layer
104
are removed.
The width of the gate
103
a
is d1, wherein the width of the gate
103
a
is the same as the pattern of the patterned photoresist layer
105
.
The size of the gate is limited to lithography technology and the characteristic of the photoresist layer; therefore it is difficult to reduce the width of the gate to 0.05 um.
SUMMARY OF THE INVENTION
The present invention is directed to a method for fabricating a T-shaped gate. The width of the gate is reduced and controlled, and the integration of the memory unit is increased, moreover, salicide is easily formed and sheet resistance is reduced.
Accordingly, the present invention provides a method for fabricating a memory unit with a T-shaped gate for a NMOS. A semiconductor substrate is provided, with a dielectric layer and a patterned hard mask having an opening are sequentially formed thereon, wherein the dielectric layer is exposed through the opening. A doped spacer is formed on a sidewall of the opening. The doped spacer is annealed to form a lightly doped area in the semiconductor substrate. The doped spacer and the dielectric layer in the opening are removed. An insulating spacer is formed on the sidewall of the opening. A gate dielectric layer is formed on the exposed semiconductor substrate in the opening, and a conducting layer is filled in the opening. The patterned hard mask layer is removed. An ion doped area is formed on a side of the lightly doped area in the semiconductor substrate.
Accordingly, the present invention provides a method for fabricating a memory unit with a T-shaped gate for a PMOS. A semiconductor substrate is provided, with a dielectric layer and a patterned hard mask layer having an opening sequentially formed thereon, wherein the dielectric layer is exposed through the opening. An N type conducting spacer is formed on a sidewall of the opening. The semiconductor substrate is thermally oxidized to form a gate dielectric layer on the semiconductor substrate and the N type conducting spacer. The opening is filled with a P type conducting layer. The patterned hard mask layer is removed. An insulating layer is formed on a sidewall of the N type conducting spacer.
Accordingly, the present invention also provides a method for fabricating a memory unit with a T-shaped gate for a CMOS. A semiconductor substrate is provided with a dielectric layer and a patterned hard mask layer having a first opening and a second opening formed thereon. The dielectric layer is exposed through the first opening and the second opening. A silicate glass spacer is formed on a sidewall of the first opening. The exposed dielectric layer in the first opening and the second opening are sequentially removed. The silicate glass spacer is annealed to form a lightly doped area under the silicate doped area. The silicate glass spacer is removed. An insulating spacer is formed on a sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. A first N type conducting spacer and a second N type conducting spacer are formed on a sidewall of the insulating spacer and the second opening respectively. A first gate dielectric layer is formed on the exposed semiconductor substrate in the first opening and the first N type conducting spacer. A second gate dielectric layer is formed on the semiconductor substrate in the second opening and the second N type conducting spacer. The first opening and the second opening are filled with a first P type conducting layer and a second P type conducting layer respectively. The patterned hard mask layer is removed. A second spacer is formed on the sidewall of the second N type conducting spacer.
REFERENCES:
patent: 5434093 (1995-07-01), Chau et al.
patent: 5714412 (1998-02-01), Liang et al.
patent: 6093945 (2000-07-01), Yang
patent: 6344995 (2002-02-01), Chen et al.
patent: 10289957 (1998-10-01), None
Chuang Ying-Cheng
Huang Chung-Lin
Lin Chi-Hui
Nanya Technology Corporation
Quintero Law Office
Vockrodt Jeff
Zarabian Amir
LandOfFree
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