Method for fabricating memory cells using chemical mechanical po

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438254, 438397, H01L 218242

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active

058343490

ABSTRACT:
A method for manufacturing an array of stacked capacitors with increased capacitance on a dynamic random access memory (DRAM) device was achieved using chemical mechanical polishing (CMP). The invention utilizes CMP to planarize a polysilicon layer in which the capacitor bottom electrodes are formed using two masking steps and a self-aligning etch-back step to form a very high density array of capacitors for DRAM devices. The method involves depositing and then planarizing a thick first polysilicon layer by CMP over a partially completed DRAM cell. A patterned silicon oxide layer with portions aligned over the node contact openings of the pass transistors (FETs) is formed. Silicon nitride sidewall spacers are formed on the vertical sidewalls of the silicon oxide and a thermal oxide is grown on the first polysilicon layer. After selectively removing the nitride spacers, the polysilicon is etched to form deep trenches with inner sidewalls for the bottom electrodes. The oxide etch mask layers are removed and a second photoresist mask is used to define the outer perimeter (sidewalls) of the array of bottom electrodes. An interelectrode dielectric layer is formed on the bottom electrodes and a second polysilicon layer is deposited and patterned to form the top electrodes and to complete the array of stacked capacitors on the DRAM device.

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