Method for fabricating memory cells and memory cell array

Details Method for fabricating memory cells and memory cell array Method for fabricating memory cells and memory cell array

2006-07-25

2006-07-25

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

07081383

ABSTRACT:
A method for producing memory cells, in which an electrically conductive substrate is provided, a trench structure or cup structure with side walls and a base is formed in or on the substrate, a first insulation layer is deposited at the side walls, a capacitor material is deposited on the base, a nanostructure is grown starting from and electrically connected to the catalyst material deposited on the base, a second insulation layer is deposited on the nanostructure and on the base, and finally an electrically conductive layer is deposited as a counterelectrode on the first insulation layer and second insulation layer.

REFERENCES:
patent: 6352902 (2002-03-01), Aitken et al.
patent: 2003/0010089 (2003-01-01), Holmes
patent: 2004/0137730 (2004-07-01), Kim et al.
patent: 2005/0095780 (2005-05-01), Gutsche et al.
patent: 2005/0196950 (2005-09-01), Steinhogl et al.

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