Method for fabricating memory cell

Details Method for fabricating memory cell Method for fabricating memory cell

2005-12-12

2009-06-02

Nguyen, Thanh (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S300000, C438S304000, C438S596000

Reexamination Certificate

active

07541241

ABSTRACT:
A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.

REFERENCES:
patent: 6869849 (2005-03-01), Kanamori
patent: 7045852 (2006-05-01), Van Duuren et al.
patent: 2005/0224860 (2005-10-01), Hendriks et al.

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