Method for fabricating mask ROM via medium current implanter

Details Method for fabricating mask ROM via medium current implanter Method for fabricating mask ROM via medium current implanter

2000-09-12

2001-07-24

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S276000

Reexamination Certificate

active

06265270

ABSTRACT:

FIELD OF INVENTION
The invention relates to a method for fabricating a mask read only memory (ROM) and, in particular, to a method for fabricating a mask ROM by implanting ROM code ions via a medium current implanter.
BACKGROUND OF INVENTION
Mask ROMs (MROMs) are widely used memory devices capable of storing permanently information. MROMs are a kind of non-volatile memory device in which stored information is not erased even if the applied electric power is removed. MROMs are mainly classified into NOR type MROMs and NAND type MROMs as defined by the circuit structure of the memory cell which is used in the device.
MROMs in which data ordered by client is written by use of a mask in a fabrication process have several advantages. First, MROMs have a simplex circuit construction in which no separate data writing circuit is required. Second, MROMs require only a simplex fabrication in which used memory cell structure requires no specific fabrication process. Third, MROMs are capable of providing various memory cell systems from which an appropriate one can be selected according to the use intended.
A widely used method for writing data into MROMs is an ion implantation method. This method performs writing of information for MROMs by use of ion implantation.
FIGS. 1A and 1B
are schematic and pictorial views respectively illustrating a memory cell array
1
in a typical MROM of the ion implantation type.
FIG. 1A
is a plan view of a layout of the memory cell array
1
.
FIG. 1B
is a circuit diagram illustrating an equivalent circuit of the memory cell array
1
.
In
FIG. 1A
, a region
2
surrounded by the dotted line represents one of a plurality of memory cells arranged in matrix manner in the memory cell array
1
. Each memory cell
2
is realized by either an N type or a P type MOS transistor.
The MROM shown in
FIG. 1A
is of the ion implantation type, in which a region
8
surrounded by the dashed line corresponds to an impurity-implanted region formed at a channel region of a MOS transistor.
In this case, the memory cell array
1
includes the MOS transistors which each has an impurity-implanted region
8
and others which each has no impurity-implanted region
8
. The MOS transistors having the impurity-implanted region
8
become transistors operating in the depletion mode corresponding to the level “1” of information. Opposite, the MOS transistors having no impurity-implanted region
8
become transistors operating in the enhancement mode corresponding to the level “0” of information.
In an MROM of the ion implantation type, the process of implanting ROM code ions must be performed after an order from client. Therefore, there is a turn around time in the fabrication of an MROM when manufacturer takes to fabricate the MROM after an order from client. Early, the process of implanting ROM code ions is performed after the formation of MOS transistors. Afterward, the successive processes are performed to complete the MROM. This results in a low productivity due to very long turn around time.
To date, a post-passivation MROM programming method, in which the process of implanting ROM code ions is performed after the formation of passivation layer, is widely applied. The improved method significantly reduces the turn around time when fabricating an MROM. However, in the method, a high current implanter is required to implant ROM code ions into semiconductor substrate through a thickness of more than 10,000 Å. It is evident that the cost of fabricating MROMs increases due to the requirement of expensive equipment. Besides, the ROM code ions with high energy (more than 500 keV) probably introduces deleterious effects into ROM devices.
U.S. Pat. No. 5,350,703 provides a method for fabricating an MROM device first by etching back partially an array of passivated MOS transistors to expose selected gate electrodes and then by implanting ROM code ions into the employed substrate to complete the information storage of ROM. However, in practical application, the fabrication method (etching back method) is difficult for manufacturers to control the etching stop point without excessive etching back. So the etching back method would cause the damage of selected transistors.
Accordingly, an objective of the invention is to fabricate post-passivation MROMs via a medium current implanter. By use of a medium current implanter, the invention reduces the cost and deleterious effects for fabricating post-passivation MROMs.
Another objective of the invention is to employ an etching back method to directly form a ROM code pattern on an array of passivated MOS transistors without the damage of selected transistors.
SUMMARY OF INVENTION
An objective of the invention is provided a method for fabricating a post-passivation programmed MROM via a medium current implanter. The inventive method is capable of shortening turn around time and enhancing productivity without the need to add expensive equipment.
A ROM code pattern is directly formed on an array of passivated MOS transistors, in the invention. The array of passivated MOS transistors is employed in an etching back process to form openings in accordance with a ROM code. The resultant structure is identified as the ROM code pattern. The ROM code ions are successfully implanted into the substrate through the openings via a medium current implanter.
According to this invention, for fabricating an MROM device, the formation of an array of MOS transistors on a semiconductor substrate is achieved. In the array of MOS transistors, a MOS transistor includes a gate oxide film, a gate electrode, a source region and a drain region. A silicon glass layer, metal electrodes and a passivation layer are sequentially formed over the array of MOS transistors. After an order from client, an etching back process is performed to remove selected portions of the passivation layer to form openings in accordance with a ROM code. The selected portions are located over the selected gate electrodes respectively. The portions of the silicon glass layer within the openings are successively etched until the remained silicon glass layer is in a predetermined thickness. ROM code ions are implanted into the substrate via a medium current implanter. The remained thickness of the etched-back silicon glass layer within the openings is employed to form the code identification on the substrate. Therefore, for fabricating the MROM, the ROM code pattern is directly formed on the passivated array of MOS transistors without the need to form another mask.
In a preferred embodiment of the invention, the remained thickness of the etched-back BPSG layer within the openings is set within a range of about 1,500 Å to 2,000 Å. The thickness of the USG layer underlying the etched-back BPSG layer within the openings is set within a range of about 1,500 Å to 2,000 Å. In this case, the P+ type of ROM code ions are successfully implanted into the substrate via the medium current implanter operating at an energy level of about 100 keV to 150 keV. Alternatively, the N+ type of ROM code ions are successfully implanted into the substrate via the medium current implanter operating at an energy level of about 250 keV to 360 keV. The medium current implanter is operated normally in the energy level of 100 keV to 360 keV. Thereby, the structure with openings mentioned above can be identified as a ROM code pattern, and the ROM code ions can be successfully implanted into the substrate through the openings and the glass layers within the openings.


REFERENCES:
patent: 5270237 (1993-12-01), Sang et al.
patent: 5350703 (1994-09-01), Lee
patent: 5665995 (1997-09-01), Hsue et al.
patent: 5681772 (1997-10-01), Chen et al.

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