Method for fabricating low-k dielectric and Cu interconnect

Details Method for fabricating low-k dielectric and Cu interconnect Method for fabricating low-k dielectric and Cu interconnect

2011-08-16

2011-08-16

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S618000, C438S622000, C438S623000

Reexamination Certificate

active

07998873

ABSTRACT:
A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

REFERENCES:
patent: 7078350 (2006-07-01), Kim et al.
patent: 7129159 (2006-10-01), America et al.
patent: 7129162 (2006-10-01), Hong et al.
patent: 2001/0017402 (2001-08-01), Usami
patent: 2005/0095869 (2005-05-01), Tao et al.
patent: 2008/0057728 (2008-03-01), Shimura et al.

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