Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-16
2001-02-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S197000
Reexamination Certificate
active
06190978
ABSTRACT:
BACKGROUND
The current patent application incorporates in its entirety the patent application entitled “Quasi-Mesh Gate Structure for lateral RF MOS Device”, Ser. No. 09/020,256, and the patent application entitled “A Source Connection for lateral RF MOS Devices”, Ser. No. 09/020,257.
Power high frequency devices have been built using a variety of semiconductor technologies. For a long time the preferred vehicle for their realization has been the NPN bipolar junction transistor (BJT). Its primary advantage was the achievable high intrinsic transconductance (g
m
) that permitted the fabrication of high power devices utilizing small silicon areas.
As processing technology improved, in the early 1970's a number of MOSFET vertical structures begun to challenge the dominance of the BJT at the lower RF frequencies, trading the cost of the large silicon area, necessary to provide the current capability in MOSFETs, for the cost of simple processing. The advantages that the MOSFET structure provided to the user were: higher power gain, ruggedness (defined as the capacity to withstand transients) and ease of biasing.
In the continuous quest for high frequency operation at high power the MOSFET structure has displaced the BJT since the early 1970's in applications where its performance has been competitive.
Recently, new RF MOS devices from several vendors have been placed on the market. The RF MOS device utilizes the standard lateral MOS device with a diffused via that connects the source and the body to the back side of the chip such that the backside becomes both electrical and thermal ground. The prior art RF MOS device structure also uses a polysilicon gate process as a compromise between the fabrication benefits of the self aligned polysilicon gate and the high frequency performance of the metal gate structure. The prior art RF MOS structure has extended the frequency of operation of MOS devices into the 2 GHz region thus covering two frequency bands of great commercial importance: the cellular and PCS/PCN mobile telephone bands.
In the incorporated U.S. patent application entitled “A Source Connection S for lateral RF MOS Devices”, Ser. No. 09/020,257, the vertical geometry design of the existing RF MOS devices was further improved. This was done by connecting the source and the body of the RF MOS device to the backside of the silicon substrate using a metal plug thus reducing the space needed for that connection. The metal plug design allows a design engineer to utilize more of the RF MOS device active area per unit chip area, to increase the output power per unity chip area, to further decrease the drain—source capacitance (C
ds
), and to increase the bandwidth (BW) of the RF MOS device in the amplifier mode of operation.
In terms of horizontal geometry, the prior art bipolar junction transistor (BJT) used two basic geometries: the interdigitated geometry and the mesh geometry. The interdigitated BJT structure is a set of parallel rows of emitters stripes placed inside a base area. The mesh geometry is similar to the interdigitated but includes connections between emitter stripes.
Traditionally, the RF MOS transistor had the BJT interdigitated horizontal geometry with polysilicon fingers (gate), drain contact in the middle, and the source on both sides. In this geometry, the current moves from the source (from the bottom) to the drain under the gate. The problem with this structure is that the signal had to feed a very long and narrow gate finger. Specifically, the ratio of the length of the gate finger (50-100)&mgr; to the width of the gate finger (1 &mgr;) was about (50-100). For the prior art polysilicon gate fingers with (50-100 squares) and with the resistivity per square of (20 &OHgr;/square), the resistivity was too high 20×100=2,000 &OHgr;, so that different portions of the gate were not fed equally. Depending on the frequency and the resistivity of the material, some portions of the gate were not used at all.
The finger also adds a sizable capacitance component to the channel. Such combination acts as a voltage divider lowering the magnitude of the effective signal entering the device.
On the other hand, all portions of a metal gate with the resistivity per square of 0.1 (&OHgr;/square) could be fed very efficiently up to very high frequencies.
Thus, one solution to this problem is to put silicide on the polysilicon gate finger, that is to put metal like tungsten (Tg), titanium (Ti), cobalt (Co), or platinum (Pl) on the polysilicon. If high enough temperature is applied, the metal and the polysilicon mix and form the silicide. The resistivity per square of the silicided gate is significantly decreased comparatively with the polysilicon gate. Indeed, the resistivity per square for the tungsten silicided gate is (2 &OHgr;/square), for the titanium silicided gate is 1 (&OHgr;/square), for the cobalt silicided gate is (1-2) (&OHgr;/square), and for the platinum silicided gate is (1-2) (&OHgr;/square).
The silicided gate is adequate for a broad range of frequencies. For instance, the silicided gate fingers in the prior art RF MOS devices could be fed very efficiently at cellular 900 MHz frequencies. However, at higher frequencies, in the range of 2 GHz needed for operation of the personal communication services devices (PCS), the long silicided gate is still not adequate because it can not be fed equally.
In the incorporated U.S. patent application “Quasi-Mesh Gate Structure for lateral RF MOS Device”, Ser. No. 09/020,256, the horizontal geometry design of the prior art RF MOS devices at high frequencies was further improved by reducing the length of the silicided gate fingers.
In the U.S. patent application entitled “METHOD FOR FABRICATING A LATERAL RF MOS DEVICE WITH A NON-DIFFUSION SOURCE—BACKSIDE CONNECTION”, Ser. No. 09/072,393, that is incorporated in its entirety in the present patent application, a method of fabrication a lateral RF MOS device having a non-diffusion source-backside connection and having an interdigitated or a quasi-mesh silicided gate structure was disclosed.
However, the method disclosed in the U.S. patent application entitled “METHOD FOR FABRICATING A LATERAL RF MOS DEVICE WITH A NON-DIFFUSION SOURCE—BACKSIDE CONNECTION”, the common problem is the electrical shorts between the polysilicon gate and the source and/or drain areas.
What is needed is the method of fabrication of lateral RF MOS devices, wherein the electrical shorts between the polysilicon gate and the source and/or drain areas are minimized, and accordingly, the yield of fabrication of lateral RF MOS devices per silicon wafer is maximized.
SUMMARY
The present invention is unique because it discloses methods of fabrication of a lateral RF MOS device having a non-diffusion source-backside connection and either interdigitated or quasi-mesh silicided gate structure, wherein the electrical shorts between the polysilicon gate and the source and/or drain areas are minimized, and accordingly, the yield of fabrication of lateral RF MOS devices per silicon wafer is maximized.
One aspect of the present invention is directed to a method of forming a lateral RF MOS device with a non-diffusion source-substrate connection starting from a substrate of a first conductivity type.
In one embodiment, the method comprises the following steps: (a) forming an epitaxial (epi) layer of a first conductivity type; (b) forming a conductive gate of the RF MOS device; (c) forming a body contact region of the RF MOS device; (d) forming a body region of the RF MOS device; (e) forming an enhanced drain drift region of the RF MOS device; (f) forming a drain region of the RF MOS device; (g) forming a source region of the RF MOS device; (h) forming a conductive plug region in the source region and in the body region of the epi layer; and (i) forming a plurality of metal contacts to an outside circuitry.
In another embodiment, a method of forming a lateral RF MOS device with a non-diffusion source-substrate connection starting from a substrate comprises the following steps: (a) providing a semicondu
Malsawma Lex H
Smith Matthew
Tankhilevich Boris G.
Xemod, Inc.
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