Method for fabricating integrated circuits having both high...

Details Method for fabricating integrated circuits having both high... Method for fabricating integrated circuits having both high...

2007-08-14

2007-08-14

Crane, Sara (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S500000

Reexamination Certificate

active

10710616

ABSTRACT:
A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.

REFERENCES:
patent: 6417044 (2002-07-01), Ono
patent: 6531363 (2003-03-01), Uchida
patent: 2002/0068406 (2002-06-01), Ishii
patent: 2003/0235960 (2003-12-01), Hayashi

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