Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-23
2002-12-31
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S291000
Reexamination Certificate
active
06500716
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the benefit of Application No. P2000-13116, filed in Korea on Mar. 15, 2000, which is hereby incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a high voltage transistor which increases a breakdown voltage.
BACKGROUND OF THE RELATED ART
Generally, a high voltage transistor is formed on a semiconductor substrate. A source/drain region and a channel are formed on the semiconductor substrate. An insulating layer and a conductive gate are sequentially formed on the channel. A drift region is formed to entirely wrap the source/drain region.
The drift region has a deep junction depth so that an electric field is diffused, thereby increasing a junction breakdown voltage due to concentration of the electric field.
A method for fabricating a related art high voltage transistor will be described with reference to the appended drawings.
FIGS. 1
a
to
1
f
are sectional views showing a method for fabricating a related art high voltage transistor.
As shown in
FIG. 1
a
, a first photoresist
12
is deposed on a p-type semiconductor substrate
11
. The first photoresist
12
is patterned by exposing and developing processes, so that a drift region is defined.
N-type impurity ions are implanted into the drift region of the semiconductor substrate
11
using the patterned first photoresist
12
as a mask, wherein the N-type impurity ions are implanted with an energy of 10 keV or less and at a dose from 1E13 to 5E14. The n-type impurity ions are diffused by a heat diffusion process of 900° C. to 100° C. so that a drift region
13
is deeply formed on a first surface of the semiconductor substrate
11
.
As shown in
FIG. 1
b
, the first photoresist
12
is eliminated, and an oxide film
14
and a nitride film
15
are sequentially formed on an entire second surface of the semiconductor substrate
11
. The oxide film
14
and the nitride film
15
corresponding to a field region are selectively eliminated by photolithography and etching process.
Channel stop ions are implanted into the exposed semiconductor substrate
11
using the oxide film
14
and the nitride film
15
as masks.
As shown in
FIG. 1
c
, a local oxidation of silicon (LOCOS) process is performed on the semiconductor substrate
11
, into which the channel ions are implanted, so that the field oxide film
16
is formed on a third surface of the semiconductor substrate
11
, and the oxide film
14
and the nitride film
15
are eliminated.
As shown in
FIG. 1
d
, ions for controlling a threshold voltage are implanted into the semiconductor substrate
11
. A gate oxide film
17
is formed on a whole fourth surface of the semiconductor substrate
11
and a polysilicon layer
18
is formed on the gate oxide film
17
.
A second photoresist
19
is deposited on the polysilicon layer
18
and is patterned by the exposing and developing processes, so that a gate region is defined.
As shown in
FIG. 1
e
, the polysilicon layer
18
and the gate oxide film
17
are selectively eliminated using the patterned second photoresist
19
as a mask, so that a gate electrode
18
a
is formed.
As shown in
FIG. 1
f
, the second photoresist
19
is eliminated, and an insulating layer is formed on an entire fifth surface of the semiconductor substrate
11
including the gate electrode
18
a
. Sidewall spacers
20
are formed on both sides of the gate electrode
18
a
by an etching-back process. N-type high-concentration impurity ions for a source/drain are implanted into an entire sixth surface of the semiconductor substrate
11
so that a source/drain impurity diffusion region
21
is formed into the sixth surface of the semiconductor substrate
11
at both sides of the gate electrode
18
a.
Accordingly, in the method for fabricating the related art high voltage transistor, drift ions implantation is performed to achieve high junction breakdown voltages and then, the drift region
13
is formed by using the heat diffusion process of 900° C. to 1100° C.
To deeply form the drift region
13
, a dopant is diffused by the heat diffusion process of 900° C. to 1100° C. In this configuration, the dopant diffuses from an edge of a diffusion window to a side thereof. Thus, a cylindrical junction is formed in the edge while a spherical junction is formed in a sharp corner of the diffusion window. This reduces a curvature of a depletion layer, thereby reducing the junction breakdown voltage. This may be known by distribution of the electric field between deep junction and shallow junction at one doping level.
In this case, the deep junction and the shallow junction have an equal depletion width to an applied reverse bias. However, in case of the shallow junction, high local electric field occurs at which lines of the electric field are further concentrated. The concentration of the lines of the electric field reduces the breakdown voltage.
Therefore, to diffuse the electric field by increasing the related art depletion width, a floating field ring or an equipotential field plate may be formed around the diffusion window.
However, there are several problems with the related art method for fabricating a high voltage transistor.
When the drift region is deeply formed by the heat diffusion process of high temperature, lateral diffusion is increased correspondingly, thereby deteriorating a short channel effect.
Furthermore, when the drift region is deeply formed by the heat diffusion process of high temperature, the high temperature process affects a junction of a low logic portion or the doping of the channel and therefore, should be initially performed.
Finally, the floating field ring or the equipotential field plate may be formed around the diffusion window so that an electric field is diffused by increasing the depletion width. However, this has disadvantages in view of a chip size.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a high voltage transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a high voltage transistor in which a breakdown voltage and a packing density are improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a high voltage transistor according to the present invention includes the steps of forming a plurality of drift regions on a semiconductor substrate of a first conductive type, implanting drift ions of a second conductive type into surfaces of the drift regions of the semiconductor substrate at a first depth, implanting drift ions of the second conductive type into the surfaces of the drift regions of the semiconductor substrate at a second depth deeper than the first depth, implanting first conductive channel stop ions into the semiconductor substrate thereby forming a space between the semiconductor substrate and the drift regions, forming a device isolation film on a surface of the semiconductor substrate into which the channel stop ions are implanted, forming a gate electrode by inserting a gate insulating film on the semiconductor substrate between the drift regions, and forming a source/drain impurity diffusion region of a second conductive type in the surface of the semiconductor substrate at both sides of the gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplar
Choi Jae Seung
Kim Sung Youn
Seo Jung Hoon
Yi Sang Bae
Brewster William M.
Dang Trung
Hyundai Electronics Industries Co,. Ltd.
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