Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-29
2001-02-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S258000
Reexamination Certificate
active
06190983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high-voltage MOS transistors, and, more particularly, to a method for providing triangle shapes of high-density plasma CVD film, thereby the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated.
2. Description of the Prior Art
As the scale of integrated circuits (ICs) has been rapidly decreased, the design and layout rule becomes more stringent. Moreover, as the integrated circuits (ICs) are fabricated to be more compact, the integration of ICs with different applications becomes indispensable.
The high voltage device can be used in TFT LCD device, in laser print head application, etc.
FIG. 1A
to
1
D show the cross section of a conventional high-voltage MOS transistor, which usually includes a silicon substrate
100
and a gate oxide
120
. Moreover, a polysilicon layer
140
is deposited over the gate oxide layer
120
. A photoresist layer is formed above the polysilicon layer
140
and the gate oxide layer
120
, wherein the photoresist layer is defined and etched to form a gate. Then, the photoresist layer is removed. Consequentially, N-type ions
160
I are implanted into the silicon substrate
100
to form N-type grad
160
therein. Moreover, the offset source/drain mask layer
180
is formed above the silicon substrate
100
, and then N
+
-type ions
200
I are implanted into the N-type grad to form source/drain region.
SUMMARY OF THE INVENTION
An object of the present invention is to substantially obviate one or more of the problems caused by limitations and disadvantages of the related art.
In accordance with the present invention, a method is provided for saving a mask process of the high-voltage MOS devices. Owing to the provided triangle shapes of high-density plasma CVD film in the high-voltage use of a method, the method can be adapted at low cost.
Another purpose of the present invention is to provide triangle shapes of high-density plasma CVD film, thereby the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated.
In the embodiment, the present invention provides for saving a mask process of the high-voltage MOS devices, substantially facilitating the high-voltage MOS devices. Owing to the provided triangle shapes of high-density plasma CVD film in the high-voltage use of a method, the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated. A substrate is provided incorporating a device, wherein the device is defined as a high-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a high-voltage MOS region. Then, a gate oxide layer is formed above the silicon substrate. Moreover, a polysilicon layer is deposited over the gate oxide layer. A photoresist layer is formed above the polysilicon layer and the gate oxide layer, wherein the photoresist layer is defined and etched to form a gate. Then, the photoresist layer is removed. Consequentially, a dielectric layer is deposited and etched above the polysilicon layer using high-density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic. N-type ions are implanted into the silicon substrate to form N-type grad therein, and then N
+
-type ions only penetrate through the flat high-density plasma CVD dielectric film and not the triangle shape high-density plasma CVD film to form source/drain regions inside the N-type grad.
REFERENCES:
patent: 5686328 (1997-11-01), Zhang et al.
patent: 5716886 (1998-02-01), Wen
patent: 5851886 (1998-12-01), Peng
patent: 6074915 (2000-06-01), Chen et al.
Dang Phuc T.
Harness & Dickey & Pierce P.L.C.
Nelms David
United Microelectronics Corp.
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