Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-13
2001-06-26
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000, C438S183000, C438S278000
Reexamination Certificate
active
06251731
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more especially, to a method for fabricating NAND-type mask ROMs.
BACKGROUND OF THE INVENTION
Read-only memories (ROMs), which are nonvolatile memories and retain their memory data whenever the power is turned off, have wide applications in the computer and electronic industry. In recent years, the portable computers and telecommunications market develop rapidly and become a major driving force in semiconductor integrated circuit's design and technology. It creates a great need of high density and high speed read-only memories for notebook computers, mobile phones, portable CD players and so on. These read-only memories are required for above systems to store permanent programs such as operating systems or applications software instead of conventional mass storage equipment.
As one of the basic nonvolatile memories, mask read-only memories (mask ROMs) is preferred for mass production but is not reprogrammable. In general, mask ROM devices are constructed by memory cells for coding data and periphery controlling devices to control the operation of the cells. Each bit of data is stored in a cell, which is usually a single N-channel transistor. There are two types of ROM array referred as NOR type array and NAND type array for storing data. The NOR type ROM array consists of a set of MOS transistors connected in parallel to bit lines and has high speed operation but low bit density due to the large cell size resulting from the need of a bit line contact to every cell. The NAND type ROM structure, in which MOS transistors connected in series and has only one bit line contact for a series of cells, can be much smaller in area and exhibits higher packing density since there are no contact hole required in each array cell.
In general, mask ROM includes MOS devices with different threshold voltage for programming. Typically, the MOS transistors served as memory cells are designed to operate at the same threshold level and usually “ON” or in a logic “1” state. Some of the cell transistors are then programmed to be “OFF” or in a logic “0” state for data writing by raising their threshold voltage. For fabricating the normally “OFF” cell transistors in accordance with the designed storage circuit, a high-dosage opposite-type ion implantation into the channel regions can be adopted to increase the threshold voltage and therefore change the logic state from “1” to “0”. The doped regions are usually referred as coding regions. Alternatively, selective thickening of the gate oxide or selective through-hole contact opening can replace the coding implantation to be the chosen programming method. Furthermore, the data writing can also be achieved by changing the transistors from enhancement mode to depletion mode.
In the U.S. Pat. No. 5,406,511 titled “MASK ROM FOR STORING PLURAL-BIT DATA”, K. Nogami illustrated two top view figures of synoptic layout to mask ROM cell structures for both NOR type and NAND type arrays. K. Tasaka illustrated in U. S. Pat. No. 5,610,092 titled “METHOD FOR FABRICATING LARGE CAPACITY NAND TYPE ROM WITH SHORT MEMORY CELL GATE LENGTH” that the cross-sectional view figures for conventional mask ROM's manufacturing processes. But as stated by C. C. Hsue, et al., in the U.S. Pat. No. 5,668,031 entitled “METHOD OF FABRICATING HIGH DENSITY FLAT CELL MASK ROM”, the mask ROM wafer with all MOS transistors built in will undergo several high temperature processes. Each high temperature process could cause the diffusion of impurities in areas such as the buried bit lines so that the spaces between two adjacent bit lines will become narrow and that will induce cell punch-through. As the need and technique of memory devices trend to high density and therefore decrease of memory cell, to diminish the spaces between source and drain electrodes or between to adjacent bit lines are necessary. The punch-through problem between two impurity areas will thus become more and more serious.
SUMMARY OF THE INVENTION
A method for fabricating high-density and high-speed NAND-type mask read-only memories is disclosed. This method utilizes an anti-reflective coating for improving the exposure accuracy. Polycide is created in the word line regions to lower the word line resistance. In addition, the present invention constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue between adjacent bit lines.
First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined by a standard photolithography process followed by an anisotropic etching. Gate oxide film is formed between the bit line regions and the dopants in the doped silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and then a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed to selectively adjust the threshold voltage of predetermined coding regions. Therefore, a conductive layer is formed on the polysilicon layer and then defined to be the word line regions. A high temperature annealing is carried out to form polycide in the word line regions, the memory is thus finished.
REFERENCES:
patent: 5710073 (1998-01-01), Jeng et al.
patent: 5747359 (1998-05-01), Yuan et al.
patent: 6048765 (2000-04-01), Wu
patent: 6057195 (2000-05-01), Wu
patent: 6091119 (2000-07-01), Wu
Acer Semiconductor Manufacturing Inc.
Elms Richard
Pyonin Adam
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