Method for fabricating floating gate

Details Method for fabricating floating gate Method for fabricating floating gate

2003-04-28

2004-07-06

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000

Reexamination Certificate

active

06759300

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor process, and more particularly to a fabrication process to form a multi-tip floating gate.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use, in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
An advantage of EPROM is that it is electrically programmed, but for erasing, requires exposure to ultraviolet (UV) light.
In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device.
EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain.
One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, normally taking just 1 to 2 seconds for the complete removal of a whole block of memory. Another advantage of flash memory is its low power consumption. The voltages of a control gate, a source, and a drain are adjusted to program or erase in a split gate flash memory.
FIGS. 1
a
to
1
c
are cross-sections of the conventional method for fabricating a floating gate of a split gate flash memory.
In
FIG. 1
a
, a silicon substrate
101
is provided. A gate oxide layer
102
, a doped polysilicon layer
103
, and a nitride layer
104
having an opening
105
are sequentially formed on the silicon substrate
101
.
In
FIG. 1
b
, the doped polysilicon layer
105
exposed by the opening
105
is oxidized to form an oxide layer
106
, and an edge of the oxide layer
106
is a Bird's Beak shape edge.
In
FIG. 1
c
, the nitride layer
104
is removed. The doped polysilicon layer
103
is anisotropically etched to form a floating gate
103
a
using the oxide layer
106
as an etching mask.
A split gate flash memory is completed after a control gate is formed on the floating gate and the silicon substrate
101
is implanted to form source/drain devices.
In the program step, high voltage is applied between the source and control gate. The high voltage applied to the source goes to the floating gate by the electric capacity coupling, and a high electric field is produced on the film gate oxide layer. The voltage is injected into the floating gate through the film gate oxide layer from the drain.
In the erase step, high voltage is applied between the drain and the control gate. A high electric field is produced on the film gate oxide layer by the electric capacity coupling. The voltage is injected into the drain through the film gate oxide layer from the floating gate, such that the gate oxide layer is damaged by the high voltage.
When the edge of the floating gate is a tip, the electrical field is easily concentrated, and the point is easily discharged. If the point discharge is increased, the erasing effect is strong.
In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices.
SUMMARY OF THE INVENTION
The present invention is directed to a method for fabricating a multi-tip floating gate to increase the erasing effect.
Accordingly, the present invention provides a method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, a first insulating layer, and a patterned hard mask layer with an opening are sequentially formed, such that the opening exposes the first insulating layer. The first insulating layer and the conducting layer are sequentially etched to form a round-cornered trench using the patterned hard mask layer as a mask. The patterned hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are sequentially removed using the second insulating layer as a mask, and the conducting layer covered by the second insulating layer remains as a floating gate.
Accordingly, the present invention also provides a method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, a first insulating layer, and a patterned hard mask layer with an opening are sequentially formed, such that the opening exposes the first insulating layer. The first insulating layer and the conducting layer are sequentially anisotropically etched to form a bottom corner trench using the patterned hard mask layer as a mask, wherein the round-cornered trench does not expose the semiconductor substrate. The patterned hard mask layer is removed. A second insulating layer is formed on the first insulating layer, and the round-cornered trench is filled with the second insulating layer, wherein the material of the second insulating layer is different from that of the first insulating layer. The second insulating layer is planarized until the first insulating layer is exposed, and the second insulating layer remains in the round-cornered trench. The first insulating layer and the exposed conducting layer are sequentially anisotropically etched until the gate dielectric layer is exposed, and the conducting layer covered by the second insulating layer remains as a floating gate.


REFERENCES:
patent: 6090668 (2000-07-01), Lin et al.
patent: 6294429 (2001-09-01), Lam et al.
patent: 6358797 (2002-03-01), Tseng
patent: 6586302 (2003-07-01), Hopper et al.
patent: 2002/0187608 (2002-12-01), Tseng
Wolf, “Silicon Processing for the VLSI Era”, vol. 1, 1986, pp. 182-184, 191-194, 539-544.

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