Method for fabricating floating gate

Details Method for fabricating floating gate Method for fabricating floating gate

2002-01-18

2002-11-19

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S734000

Reexamination Certificate

active

06482728

ABSTRACT:

CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 2001-2984, filed on Jan. 18, 2001, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating non-volatile memory devices and, more particularly, to a method for fabricating a floating gate.
2. Description of the Related Art
Generally, non-volatile memory devices comprise a stack gate structure including a floating gate for storing electric charge, and a control gate for accessing a memory for a read or write operation. It is known that the charge storing capability of the non-volatile memory devices relates to a coupling ratio C/R.
The coupling ratio C/R is a ratio, for example, between a tunnel oxide capacitance and an oxide-nitride-oxide ONO capacitance, and more particularly the ratio of the voltage applied to the control gate and the voltage coupled to the floating gate.
When storing data to a cell of the non-volatile memory device, the coupling ratio C/R (V
fg
/V
cd
, is C
2
(C
2
+C
1
), normally having a value of about 0.55 to 0.65. When erasing data from the cell of the non-volatile memory device, the coupling ratio C/R (V
fg
/V
channel
) is C
1
/(C
2
+C
1
), normally having a value of about 0.35 to 0.45. In this case, the V
fg
is a voltage applied to the floating gate, the V
cg
is a voltage applied to the control gate, and the V
channel
is a voltage applied to a channel. The capacitance C
1
is a coupling capacitance between a substrate and the floating gate and the capacitance C
2
is a coupling capacitance between the floating gate and the control gate.
Referring to
FIG. 1
, when a cell pitch is large, the floating gate having more than a predetermined coupling ratio C/R can be fabricated even when the height of the floating gate is about 1000 Å lower than the normal case. If the height of the floating gate is low, there is an advantage in that the sidewall of the floating gate can be vertically etched and this removes the possibility of a bridge between the floating gates. Also, the problem of the field regions being damaged during etching of an oxide-nitride-nitride (ONO) layer can be avoided.
However, as the cell pitch decreases, the height of the floating gate also increases to maintain the predetermined amount of the coupling ratio C/R. However, as the height of the floating gate increases, for example, about 3000 Å, the field regions can be damaged during etching of the ONO layer.
Referring to
FIG. 2
, to solve the above-mentioned problem, the sidewalls of the floating gates are sloped to lower the vertical thickness of the ONO layer. Therefore, the etching amount of the ONO layer is reduced so that damage to the field regions can be prevented.
However, sloped sidewalls of the floating gates increase the possibility of a bridge between the floating gates. Therefore, the sloped sidewall structure may be improper for the floating gate of the non-volatile memory devices having a smaller cell pitch (smaller spacing).
FIGS. 3 through 6
are cross sectional views illustrating the conventional method for fabricating a floating gate.
As shown in
FIG. 3
, a field region or device isolation layer
3
and a tunneling oxide is formed on a substrate
1
using conventional techniques. A lower polysilicon layer
7
, a nitride layer
9
for forming an etching mask, and a sacrificial polysilicon layer
13
are sequentially formed on a substrate
1
.
Referring to
FIG. 4
, after etching the lower polysilicon layer
7
and the nitride layer
9
, a nitride layer is deposited over the resulting structure. Next, the deposited nitride layer is anisotropically etched to form sidewall spacers
15
on the lower polysilicon layer
7
.
As shown in
FIG. 5
, using the sidewall spacer
15
as an etching mask, the lower polysilicon layer
7
and the sacrificial polysilicon layer
13
are etched together to form a floating gate pattern
7
′ having the width of 0.1 &mgr;m.
Referring to
FIG. 6
, the nitride layer
9
and the sidewall spacer
15
are removed by an etchant such as a phosphorous acid, and an inter-gate dielectric layer
10
of an ONO structure and a control gate
17
are formed over the floating gate pattern.
Then, portions of the floating gate pattern
7
and the gate insulation layer
10
are removed for source and drain areas of memory cells as shown in FIG.
7
.
However, the above-mentioned conventional process is too complicated and generates damage to the polysilicon layer
7
when the phosphorous acid removes the nitride layer
9
and the sidewall spacers
15
. Therefore, current leakage can occur through the inter-gate dielectric layer
10
. Additionally, as shown in
FIG. 6
, because the conventional process performs an over-etching for complete removal of the inter-gate dielectric layer
10
formed in the sidewall of the floating gate
7
. Therefore, as shown in
FIG. 7
, when the device isolation layer
3
is damaged in the area A, the subsequent ion implanting process generates a channel below the device isolation layer
3
and this deteriorates the device isolation characteristic.
SUMMARY OF THE INVENTION
To overcome the above-described problems, the present invention provide a method for fabricating a floating gate for non-volatile memory devices having a smaller cell pitch.
According to one embodiment of the present invention, a conductive layer having upper and lower portions is formed over a substrate with field regions formed therein. A hard mask layer is formed over the conductive layer. Next, a photoresist pattern is formed over the hard mask layer. The hard mask layer is etched to form a hard mask pattern, using the photoresist pattern as an etching mask. The upper portion of the conductive layer is slope-etched, leaving the lower portion of the conductive layer intact, using the photoresist pattern as an etching mask. The slope-etched upper portion of the conductive layer is vertically etched and the lower portion of the conductive layer is concurrently slope-etched, using the hard pattern as an etching mask.
According to another embodiment of the present invention, a conductive layer having upper and lower portions is formed over a substrate with field regions formed therein. A hard mask layer is formed overlying the conductive layer. A photoresist pattern is formed on hard mask layer. Next, slope etching of the hard mask layer to form hard mask pattern having sloped sidewalls, using the photoresist pattern as an etching mask, is performed. Then, the photoresist pattern is removed. The upper portion of the conductive layer is vertically etched, leaving the lower portion of the conductive layer un-etched or intact, using the hard mask pattern as an etching mask. The remaining lower portion of the conductive layer is vertically etched using an etch chemistry having substantially no etch selectivity between the hard mask layer and the conductive layer and sloping etching the upper portion of the conductive layer.
With the embodiments of the present invention, a bridge between floating gates can be reduced, and field loss can be reduced during processing steps such as an ONO etching process.


REFERENCES:
patent: 6284637 (2001-09-01), Chhagan et al.
patent: 6368917 (2002-04-01), Kalnitsky et al.

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