Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-19
2002-07-09
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S589000
Reexamination Certificate
active
06417048
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for fabricating a flash memory with recessed floating gates, and more particular, to a method for fabricating a more reliable flash memory characterized in that the bird beak is eliminated and the buried bit line region is uniformly doped.
2. Description of the Prior Art
The basic configuration of a flash memory, in general, is composed of two major portions: the memory cell array and the peripheral circuit. The memory cell array for data storage is constructed by a plurality of memory cells regularly arranged in an array based on the intersected word lines and bit lines. The peripheral circuit provides the flash memory with functions such as power supply and data processing during operation. Flash memories can be classified according to the gate electrode structures. In a flash memory with stacked control gates, a floating gate is capacitively coupled to a control gate that is stacked above it.
In the prior art, for example, the U.S. Pat. No. 6,084,265 discloses a high-density shallow trench contact less nonvolatile memory. Please refer to
FIG. 1
to
FIG. 8
, in which the method for fabrication is schematically illustrated. To begin with, there is provided a semiconductor substrate
2
, on which a silicon oxide layer is formed as a pad oxide
4
and a silicon nitride layer
6
is formed as a mask for oxidation. By using a photoresist layer
8
, the buried bit line region is defined by a standard photolithography process. An anisotropic etching follows to etch the silicon layer and then the n+impurity ions are implanted to form bit line regions
10
using the patterned photoresist
8
as a mask.
After stripping the photoresist layer
8
, a high temperature steam oxidation process (also known as LOCal Oxidation of Silicon, LOCOS) is used to grow a thick field oxide
12
using the silicon nitride layer as a mask, and the doped ions are activated and driven in to form the buried bit lines
10
simultaneously. The masking silicon nitride layer
6
and the pad oxide layer
4
are then removed, and the silicon substrate
2
is recessed by using the field oxide
12
as an etching mask. After rounding the trench corners by using thermal oxidation and etching back processes, a thin silicon oxynitride film
14
is regrown over the substrate
2
.
Finally, an insitu doped polysilicon film is deposited to refill the trench region and then etch back by using a chemical mechanical polishing (CMP) process to form the floating gates
16
adjacent to the buried bit lines.
However, it is transparent that the bird beak occurs during the formation of the field oxide
12
by the high temperature steam oxidation process (LOCOS), leading to a non-uniform doping in the doped bit line regions
10
. On the other hand, the lateral diffusion due to the bird beak also irregularly reduces the effective width of the floating gates to be formed. Therefore, the prior art has the problems such as complexity in fabrication, low yield and high cost due to poor fabrication reliability.
Therefore, the present invention provides a method for fabricating a flash memory with recessed floating gates, which is used to overcome the problems in the prior art and improve, the reliability of the flash memory.
SUMMARY OF THE INVENTION
It is the primary object of the present invention to provide a method for fabricating a flash memory with recessed floating gates so that the bird beak is eliminated, the complexity in fabrication is reduced and the reliability is improved.
It is another object of the present invention to provide a method for fabricating a flash memory with recessed floating gates, in which a two-step trench formation process is employed so as to obtain uniformly doped buried bit line regions.
In order to achieve the foregoing objects, the present invention provides a method for fabricating a flash memory with recessed floating gates, comprising the steps of:
providing a semiconductor substrate, on which a pad oxide layer and a first dielectric layer are formed in turn;
patterning said first dielectric layer by anisotropic etching, so as to form a plurality of trenches for recessed floating gates;
implanting ions into said semiconductor substrate, so as to define a plurality of bit line regions;
filling said plurality of trenches for recessed floating gates by depositing a second dielectric layer, which is to be planarized by chemical mechanical polishing (CMP);
removing said first dielectric layer;
forming a plurality of trenches by etching by using said second dielectric layer as an etching mask;
forming a tunnel dielectric layer on the top surface of said semiconductor substrate and said plurality of trenches; and
filling said plurality of trenches by depositing a first conductive layer, which is to be planarized by chemical mechanical polishing (CMP), so as to form recessed floating gates.
The present invention provides a method for fabricating a flash memory with recessed floating gates, further comprising the steps of:
depositing a third dielectric layer;
depositing a second conductive layer; and
patterning said second conductive layer, so as to form control gates.
REFERENCES:
patent: 5229312 (1993-07-01), Mukherjee et al.
patent: 6084265 (2000-07-01), Wu
patent: 6153467 (2000-11-01), Wu
patent: 2001/0046736 (2001-11-01), Fu
patent: 64-53463 (1989-03-01), None
Chaudhari Chandra
Troxell Law Office PLLC
Vanguard International Semiconductor Corporation
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