Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-25
2001-02-27
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S589000
Reexamination Certificate
active
06194271
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a memory device. More particularly, the present invention relates to a method for fabricating a flash memory.
2. Description of the Related Art
Conventional flash memory is a type of erasable programmable read-only memory (EPROM). There have been many articles written about flash memories. In general, the gate of a flash memory includes a polysilicon floating gate, which is used for storing electric charges, and a control gate, which is used for controlling data access. Therefore, EPROM normally has two gate terminals with the floating gate located below the control gate. The control gate and the word line are usually connected, and the floating gate is usually in a “floating” state. In other words, the floating gate is not in contact with any other circuits. An outstanding property of flash memory is its ability to perform a fast, block-by-block memory erase instead of the slow, bit-by-bit memory erase as in conventional EPROM. Consequently, operation speed of a flash memory is very fast. Often, the entire memory can be erased within one or two seconds.
FIGS. 1A through 1C
are schematic, top view diagrams used to depict steps in a conventional method for fabricating a flash memory.
FIGS. 2A through 2C
are schematic, cross-sectional views of
FIGS. 1A through 1C
along a line II—II.
Referring to
FIGS. 1A and 2A
, a shallow trench isolation structure
102
is formed in a provided substrate
100
to define an active region
104
.
Referring to
FIGS. 1B and 2B
, a tunneling oxide layer
106
and a patterned gate conductive layer
108
are formed in sequence on the active region
104
.
Referring to
FIGS. 1C and 2C
, a silicon-oxy-nitride layer
110
and a polysilicon layer
112
are formed in sequence on the gate conductive layer
108
by chemical vapor deposition. The polysilicon layer
112
, the silicon-oxy-nitride layer
110
and the gate conductive layer
108
are patterned to form a gate
114
, wherein the polysilicon layer
112
is a control gate and the conductive layer
108
is a floating gate. An ion implantation process is performed to form a source/drain region
116
,
118
in the substrate
100
.
FIG. 3
is a schematic, top view of FIG.
1
C.
Referring to
FIG. 3
, the shallow trench isolation structure
102
and the active region
104
are formed before forming the gate conductive layer
108
. Thus, a misalignment problem occurs while forming the gate conductive layer
108
. In general, the width
124
of the gate conductive layer
108
is formed larger than the one of the active region
104
, so that the edge of the conductive layer
108
overlaps with the shallow trench isolation structure
102
(denoted by the reference numeral
120
). The misalignment problem is avoided, however it is difficult to increase the integration of the devices.
Similarly, the misalignment problem also occurs while forming the polysilicon layer
112
. The area overlapped by the active region
104
and the conductive layer
108
is changed because of the misalignment problem (denoted by the reference numeral
122
). Thus, the coupling ratio of the adjacent memory cells is different. An odd-even effect occurs.
In order to increase the integration of the devices, the distance
128
between the shallow trench isolation structures
102
must be shorter. However, the source/drain region
116
is smaller when the distance
128
between the shallow trench isolation structures
102
is shorter. Thus, the resistance of the source/drain region
116
is increased. Also, the distance
126
between the polysilicon layers
112
is limited by the distance
128
between the shallow trench isolation structures
102
, and it is difficult to increase the integration of the devices.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for fabricating a flash memory that avoids the misalignment problem and the odd-even effect.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating a flash memory. The method for fabricating this flash memory includes the following steps. A tunneling oxide layer, a first conductive layer, a first mask layer and a first oxide layer are formed in sequence on a provided substrate. The first conductive layer, the first mask layer and the first oxide layer are patterned to form a gate. A conformal, second oxide layer is formed over the substrate. A spacer is formed on the second oxide layer. A first doping process is performed by using the gate, the second oxide layer and the spacer as a mask to form a first doped region in the substrate. The spacer is removed. A patterned second mask layer is formed over the substrate, wherein the second mask layer crosses the gate vertically. A shallow trench isolation structure is formed by using the gate and the second mask layer as a mask. A first active region and a second active region are formed. The first mask layer and the second mask layer are removed to expose the first conductive layer. A dielectric layer and a second conductive layer are formed over the substrate. The second conductive layer, the dielectric layer and the gate are patterned to form a control gate and a floating gate, wherein a portion of the control gate overlap with the second active region. A second doping process is performed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5559048 (1996-09-01), Inoue
patent: 5770501 (1998-06-01), Hong
Ghandi, pp. 420-422, 427-429,432-434, 1983.
Ko Joe
Lin Chih-Hung
Chaudhari Chandra
Huang Jiawei
J C Patents
United Semiconductor Corp.
LandOfFree
Method for fabricating flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating flash memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2600948