Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-20
2001-12-11
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S972000
Reexamination Certificate
active
06329246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a flash memory. More particularly, the present invention relates to a method for fabricating a flash memory having a bipolar junction transistor used to do an erase operation.
2. Description of the Related Art
The basic operations of a memory device are write data and read data. The write operation of a flash memory includes a program operation and an erase operation. These two operations are performed by adjusting the threshold voltage of a floating gate. The data stored in the flash memory is changed by performing the program operation and the erase operation.
Fowler-Nordheim tunneling theory is used to perform the erase operation in a p-channel flash memory. Channel hot carrier injection theory or Band-to-Band tunneling theory is used to perform the program operation.
The drawbacks of using Fowler-Nordheim tunneling for the erase operation are low operation efficiency, poor endurance capability, etc.
FIG. 1
is a schematic, cross-sectional diagram used to depict the erase operation of a conventional flash memory.
Referring to
FIG. 1
, a control gate voltage (V
eg
) is much larger than 0V while performing the erase operation. A drain voltage (V
d
) and a source voltage (V
g
) are floating, thus no hot electrons flow between a source region and a drain region. The substrate voltage (V
sub
) is 0V or negative bias. Electrons in the channel tunnel to a floating gate because of Fowler-Nordheim tunneling.
In the method mentioned above, the electrons in the channel tunnel to the floating gate because of a high electrical field produced by the control gate voltage (V
eg
) and the substrate voltage (V
sub
). A tunneling oxide layer between the substrate and the floating gate suffers the high electrical field, so that the lifetime and reliability of the tunneling oxide layer are affected.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a flash memory that avoids a tunneling oxide layer from a high electrical field and decreases the erasure time.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, in one aspect, the invention provides a method of fabricating a flash memory. The method of fabricating a flash memory includes the following steps. A P-well is formed in an n-type substrate. An N-well is formed in the P-well. Thus, a bipolar junction transistor is made of the substrate, the P-well and the N-well. A source region and a drain region are formed in the N-well. A tunneling oxide layer, a floating gate, a dielectric layer and a control gate are formed in sequence on the substrate between the source region and the drain region. In one preferred embodiment of the present invention, a first terminal having the second conductive type, a second terminal having the first conductive type and the third terminal having the first conductive type are formed in the first well, the second well and the substrate, respectively.
In another one aspect, the present invention provides an erasure method for a flash memory having a first well and a second well in a substrate, and a control gate and a floating gate on the substrate. A first terminal, a second terminal and a third terminal are respectively formed in the first well, the second well and the substrate, and a source region and a drain region are formed in the second well. The present erasure method comprises the steps of applying a reverse bias to the first terminal and the second terminal respectively in the first well and second well in the substrate; applying a forward bias to the second terminal and the third terminal respectively in the second well and the substrate; applying a positive voltage to the control gate; and applying a floating source voltage and a floating drain voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5411908 (1995-05-01), Santin et al.
patent: 5453393 (1995-09-01), Bergemont
patent: 5712178 (1998-01-01), Cho et al.
patent: 6043123 (2000-03-01), Wang et al.
patent: 6071778 (2000-06-01), Bez et al.
patent: 6091101 (2000-07-01), Wang
Booth Richard
United Microelectronics Corp.
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