Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-05
2003-04-01
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06541342
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for fabricating an element isolating film of a semiconductor device which can efficiently control an element isolating length according to an epitaxial process.
2. Description of the Background Art
Recently, the DRAM has been highly integrated as a result of strong demands for chip miniaturization. Therefore, a process for forming an abrupt transient isolating film such as a shallow trench isolation (STI) process has been suggested to improve an element isolating property between transistors and improve integration of a device.
As compared with the general LOCOS process, the STI process has an improved abrupt transient profile, and thus obtains a number of chips in one wafer.
A conventional method for fabricating an element isolating film and a structure of the same will now be described with reference to
FIGS. 1 through 5
.
FIGS. 1
to
5
are cross-sectional diagrams illustrating sequential steps of the conventional method for fabricating the element isolating film, and the structure thereof.
Referring to
FIG. 1
, a pad oxide film
2
and a pad nitride film
3
are sequentially deposited on a semiconductor substrate
1
. Here, the pad nitride film
3
is used as a barrier film in the succeeding STI process.
Although not illustrated, a photoresist film (not shown) is coated on the pad nitride film
3
, and selectively patterned according to exposure and development processes of a photolithography process, thereby forming a photoresist film pattern (not shown) on the pad nitride film
3
.
As illustrated in
FIG. 1
, the pad nitride film
3
and the pad oxide film
2
are selectively patterned by using the photoresist film pattern as a mask, to expose an element isolating film region of the semiconductor substrate
1
.
Thereafter, the exposed semiconductor substrate
1
is etched by using the patterned pad nitride film
3
as a mask, thereby forming a trench
4
for forming the element isolating film as shown in FIG.
2
.
As depicted in
FIG. 3
, an oxide film
5
is deposited over the resultant structure including the trench
4
, to fill up the trench
4
.
As shown in
FIG. 4
, the oxide film
5
filling up the trench
4
is planarized according to a chemical mechanical polishing process.
Referring to
FIG. 5
, the pad nitride film
3
and the pad oxide film
2
are removed by using an etching solution such as phosphoric acid, thereby forming the element isolating film
5
a
. Therefore, fabrication of the element isolating film has been finished.
However, the conventional method for fabricating the element isolating film has a serious disadvantage in that an element isolating length is gradually decreased as an ion implantation density is increased to improve integration of the device, and thus an element isolating property is deteriorated.
That is, a distance between adjacent devices is shortened due to decrease of the element isolating length. As a result, leakage current flowing through the lower portion of the element isolating film influences the adjacent device, which results in a poor operation of the device.
Moreover, the Kink effect may be generated due to a structural problem of the STI process. That is, the upper edge portions of the trench have a sharp profile in the STI process. The sharpened portions are easily exposed to an electric field of a gate unit, thus lowering a threshold voltage. Accordingly, the device is operated in an off state.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method for fabricating an element isolating film of a semiconductor device which can achieve high integration of the semiconductor device without negatively affecting the design rule, by efficiently controlling an element isolating length according to an epitaxial process, and a structure of the same.
Another object of the present invention is to provide a method for fabricating an element isolating film of a semiconductor device which can increase a number of unit chips in one wafer, by obtaining a sufficient element region through improvement of the STI process, and a structure of the same.
Yet another object of the present invention is to provide a method for fabricating an element isolating film of a semiconductor device which can improve an electrical property of the device by reducing the Kink effect in the STI process, and a structure of the same.
In order to achieve the above-described objects of the present invention, there is provided a method for fabricating an element isolating film of a semiconductor device, including the steps of: forming a trench in a semiconductor substrate; forming a sidewall spacer at a side wall of the trench; forming a silicon layer on the semiconductor substrate exposed at a bottom surface of the trench; forming at least one groove portion en in the bottom surface of the trench by removing the sidewall spacer; and forming an element isolating film in the trench.
According to another aspect of the present invention, a method for fabricating an element isolating film of a semiconductor device includes steps of: forming a trench in a semiconductor substrate; forming a sidewall spacer at a side wall of the trench; forming a epitaxial layer on the semiconductor substrate exposed at a bottom surface of the trench; forming at least one groove portion in the bottom surface of the trench by removing the sidewall spacer; and forming an element isolating film in the trench.
According to another aspect of the present invention, a method for fabricating an element isolating film of a semiconductor device includes the steps of: forming a pad oxide film and then a pad nitride film over a semiconductor substrate; exposing an element isolating film region of the semiconductor substrate by patterning the pad nitride film and the pad oxide film; forming a trench in the semiconductor substrate by patterning the exposed element isolating film region forming a sidewall spacer at a side wall of the trench; forming an epitaxial layer on a bottom surface of the trench; forming at least one groove portion in the bottom surface of the trench by removing the sidewall spacer and excessively etching the pad oxide film; making the excessively-etched portion of the pad oxide film rounded according to an oxidation process; forming a high density plasma oxide film over the resultant structure including the trench to fill up the trench; planarizing the plasma oxide film according to a chemical mechanical polishing process; and sequentially removing the pad nitride film and the pad oxide film.
REFERENCES:
patent: 5923073 (1999-07-01), Aoki et al.
patent: 5926721 (1999-07-01), Hong et al.
patent: 6074927 (2000-06-01), Kepler et al.
patent: 6153479 (2000-11-01), Lin et al.
patent: 6180466 (2001-01-01), Ibok
patent: 6291353 (2001-09-01), Muller et al.
patent: 6306723 (2001-10-01), Chen et al.
Hynix / Semiconductor Inc.
Le Thao P
Nelms David
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