Method for fabricating electrostatic discharge protection device

Details Method for fabricating electrostatic discharge protection device Method for fabricating electrostatic discharge protection device

1999-03-15

2000-04-18

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438328, 438419, 438983, 257355, 257606, H01L 2362

Patent

active

060514574

ABSTRACT:
An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the cathode and the N+ buried layer; an anode coupled to the N+ buried layer with a P area formed between the anode and the N+ buried layer; and a first P+ buried layer implanted in the N+ buried layer and below the P area to form a Zener diode. In an alternative embodiment, the ESD device may be incorporated in an integrated circuit with an active component.

REFERENCES:
patent: 4683483 (1987-07-01), Burmham
patent: 5336920 (1994-08-01), Jimenez
patent: 5416351 (1995-05-01), Ito et al.
patent: 5883414 (1999-05-01), Ito
Ito, et al., "A Fully Complementary BiCMOS Technology for 10 V Mixed-Signal Circuit Applications," IEEE Transactions on Electron Devices, vol. 41, No. 7, pp: 1149-1160 (Jul. 1994).

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