Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-03-13
2003-03-25
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S697000, C438S700000, C438S712000, C438S719000, C438S724000, C438S725000
Reexamination Certificate
active
06537917
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a electrically insulating layer, more particularly, to the method for fabricating a electrically insulating layer by using the different etching rates in etching oxide and etching nitride. The surface of the electrically insulating layer, which is formed by using the present invention method, is flatter to increase the window of the back-end processes and the qualities of the products.
2. Description of the Prior Art
In the continual improvement of semiconductor integrated circuit fabrication techniques, the number of devices that can be packed onto a semiconductor chip has increased greatly, while the geometric dimensions of the individual device has been markedly reduced. In today's fabricating process, the feature size has shrunk into the sub-micron range. In such high-density chips, each of the elements must be isolated properly in order to obtain good electrical characteristics. Device isolation technology has been developed to fulfill the above requirement, the main purpose of which is to provide good insulation between the elements using a smaller isolation area so that there is additional space for building more elements.
Referring to
FIG. 1
, at first a wafer, which comprises a substrate
10
, is provided and a silicon layer
20
is formed on the substrate
10
. The material of the substrate
10
can be the silicon substrate and the material of the silicon layer
20
can be the poly-silicon. Next, a nitride layer
30
is formed on the silicon layer
20
. The material of the nitride layer can be silicon nitride to be the mask. Then a nitride oxide layer
40
is formed on the nitride layer
30
to be the anti-reflective layer. This anti-reflective layer can increase the qualities of the photolithography process and the silicon nitride oxide is usually used to be the material of the nitride oxide layer
40
.
Referring to
FIG. 2
, after deciding the location of the elements and the insulating layers on the nitride oxide layer
40
, the plural trenches are formed on the wafer by using the photolithography and etching processes. The substrates are showed at the bottom of the trenches. Referring to
FIG. 3
, oxide is filled into the trench and is filled of the trench to fabricate the oxide layer
50
to be the electrically insulating layer. The chemical mechanical polishing (CMP) process is usually used to fabricate the oxide layer
50
. Tetraethylorthosilicate (TEOS) or the mixture which comprises ozone and tetraethylorthosilicate are usually used to be the material of the oxide layer
50
.
Referring to
FIG. 4
, then the nitride oxide layer
40
and the oxide layer
50
which is over deposition are removed by using the etching back method or the chemical mechanical polishing method. The etching back method is usually used in this process and the etching rate of the oxide layer
50
is higher than the rate of the nitride oxide layer
40
. In according to ensure the nitride oxide layer
40
is removed completely, the over etching way is usually used to etch the part of the nitride layer. Referring to
FIG. 5
, after the nitride layer
30
is removed, the electrically insulating layer is fabricated on the wafer to insulate the elements which are on the wafer and to avoid the leakage defects.
Following the advancements of the semiconductor process, the width of the line is smaller and smaller. Therefore, the electrically insulating layer, which is formed by using the traditional technology, will occur several defects to affect the qualities of the semiconductor. When the oxide layer is deposited, the conformity characteristic of the oxide layer will cause a indention curve line which is formed between the interface which is between the nitride layer and the silicon layer and the interface which is between the nitride layer and the nitride oxide layer. After passing through the etching back process or the chemical mechanical polishing process, the curve line will make the surface of the electrically insulating layer show sharp corners on both sides. These sharp corners will cause the serious effects in the follow-up film deposition process to occur the break problems in the film at the place of the sharp corners. Therefore, the present invention must be used to make the flatter surface of the electrically insulating layer.
Because the sharp corner is formed, the step height between the silicon layer and the electrically insulating layer will become higher after the nitride layer is removed. This condition will make the window become not enough and will need to cost more time in the follow-up etching process. Therefore, the present invention must be used to avoid the sharp corners to be produced to increase the efficiency of the whole process.
When the traditional technology is used to fabricate the electrically insulating layer, the indention curve line will be formed between the interface which is between the nitride layer and the silicon layer and the interface which is between the nitride layer and the nitride oxide layer. After passing through the etching back process or the chemical mechanical polishing process, the curve line will make the effective thickness of the electrically insulating layer become thinner to reduce the ability of the electrically insulating layer in resisting the diffusion ions in the follow-up process. This condition will reduce the qualities of the products. Therefore, the present invention must be used to decrease the radian of the indention curve.
SUMMARY OF THE INVENTION
In accordance with the above-mentioned invention backgrounds, the traditional method can not solve the defects in forming the sharp corners on the surface of the electrically insulating layer. The present invention provides a method for forming the flatter surface of the electrically insulating layer by using the different etching rates in etching oxide and etching nitride in the two steps etching process to increase the qualities of the products.
The second objective of this invention is to increase the width of the follow-up process by using the different etching rates in etching oxide and etching nitride in the two steps etching process to form the flatter surface of the electrically insulating layer.
The third objective of this invention is to increase the effective thickness of the electrically insulating layer and to increase the ability of the electrically insulating layer in resisting the diffusion ions in the follow-up process by using the different etching rates in etching oxide and etching nitride in the two steps etching process to form the flatter surface of the electrically insulating layer.
The fourth objective of this invention is to increase the efficiency of the whole process by using the different etching rates in etching oxide and etching nitride in the two steps etching process to form the flatter surface of the electrically insulating layer.
It is a further objective of this invention is to decrease the production costs by using the different etching rates in etching oxide and etching nitride in the two steps etching process to form the flatter surface of the electrically insulating layer.
In according to the foregoing objectives, the present invention provides a method for forming the flatter surface of the electrically insulating layer by using the different etching rates in etching oxide and etching nitride in the two steps etching process. The flatter surface of the electrically insulating layer will avoid to show the sharp corners on the both sides of the surface and will avoid to cause the break problems in the film at the place of the sharp corners in the follow-up film deposition process. This condition can increase the qualities of the semiconductor products and the width of the follow-up process. The present invention can also use the flatter surface of the electrically insulating layer to increase the effective thickness of the electrically insulating layer and to increase the ability of the electrically insulating layer in resisting t
Chen Chien-Wei
Lai Jiun-Ren
Macronix International Co. Ltd.
Tran Binh X.
Utech Benjamin L.
LandOfFree
Method for fabricating electrically insulating layers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating electrically insulating layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating electrically insulating layers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3069179