Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-07
1998-04-28
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438239, 438240, 438255, 438396, 438398, H01L 218242
Patent
active
057443874
ABSTRACT:
A method for making DRAM devices having a flatter topography was achieved. A single masking step is used to concurrently etch bit line and capacitor node contact openings. The method involves forming LDD-FETs in the memory cell areas from a patterned first polysilicon layer. A second insulating layer is deposited and planarized. Bit line and capacitor node contact openings are concurrently etched in the second insulating layer to the FET source/drain contact areas. A second polysilicon layer, a tungsten silicide layer, and a third insulating layer are deposited and patterned to form bit lines extending over and into the bit line contact openings while leaving portions of the second polysilicon layer in the node contact openings to form node contacts. A third patterned polysilicon layer forms the bottom electrodes over the capacitor node contact openings adjacent to the bit lines. A thin interelectrode dielectric layer is formed on the bottom electrodes, and a patterned fourth polysilicon layer forms the capacitor top electrodes adjacent to the bit lines. This provides a flatter topography for the DRAM devices.
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Ackerman Stephen B.
Bowers Jr. Charles L.
Gurley Lynne A.
Saile George O.
Vanguard International Semiconductor Corporation
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