Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-29
1999-01-12
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
428253, H01L 218242
Patent
active
058588299
ABSTRACT:
A method for making DRAM cells with minimum active device areas (cell areas) using novel sidewall-spacer bit lines is achieved. A trench is etched in an insulating layer aligned over the device areas and orthogonal to the gate electrodes, and extending over the first and second source/drain areas. A conducting layer is deposited and etched back to form sidewall-spacer bit lines. A planar second insulating layer is formed in which bit line contact openings are etched between the sidewall-spacer bit lines to the first source/drain areas. The contact openings are filled with a third conducting layer to form the bit line contacts. A third insulating layer is deposited and capacitor node contact openings are etched between the sidewall-spacer bit lines and to the second source/drain areas. An insulating layer is deposited and etched back to insulate the sidewall-spacer bit lines in the node contact openings and a fourth con-ducting layer is deposited and etched back to form the node contacts. By this self-aligned method, the minimum unit cell area (device area) can be reduced to about 6F.sup.2, where F is the minimum feature size for the current technology. Any one of the current stacked capacitor structures, such as crown, fin-shaped, and the like, can now be built on the node contacts to provide memory cells with increased packing density.
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Ackerman Stephen B.
Chang Joni
Saile George O.
Vanguard International Semiconductor Corporation
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