Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-14
2001-08-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S240000, C438S241000, C438S242000, C438S253000, C438S254000, C438S256000, C438S396000, C438S397000, C438S398000, C438S399000
Reexamination Certificate
active
06281073
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for fabricating a bit line and a capacitor of a dynamic random access memory DRAM cell.
2. Description of the Background Art A conventional method for fabricating a dynamic random access memory DRAM cell will now be described with reference to
FIGS. 1
a
to
1
k.
As illustrated in
FIG. 1
a
, a trench is formed at an upper portion of a semiconductor substrate
1
, and filled with an insulation material, thereby forming a field insulation film
3
. A gate
9
consisting of a gate insulation film
5
and a gate electrode
7
is formed on the semiconductor substrate
1
divided into an active region A and an isolation region B by the field insulation film
3
. An insulation film is formed on the semiconductor substrate
1
including the gate
9
, and an anisotropic etching process is performed thereon without a mask, thereby forming first sidewall spacers
11
at both side portions of the gate
9
. The first sidewall spacers
11
serve to insulate a storage node contact plug
17
and a bit line
23
from the gate
9
during a process of forming the storage node contact plug
17
and the bit line
23
. A first doped region
12
a
and a second doped region
12
b
operated as a source and a drain are formed at the upper portion of the semiconductor substrate
1
exposed between the gates
9
in accordance with an ion implantation process, by using the gate
9
and the first sidewall spacers
11
as masks.
As shown in
FIG. 1
b
, a first insulation film is formed over the semiconductor substrate
1
, and patterned according to a photoetching process using a photoresist film (not shown) so that the upper surface of the first doped region
12
a
between the gates
9
can be exposed, thereby forming a first insulation film pattern
13
. As a result, a first contact hole
15
is formed.
Referring to
FIG. 1
c
, a first conductive film consisting of a polycrystalline silicon is formed in the first contact hole
15
and on the first insulation film
13
. Thereafter, an etching process or a chemical mechanical polishing CMP process is carried out until the upper surface of the first insulation film
13
is exposed, thereby forming the storage node contact plug
17
consisting of the first conductive film. The storage node contact plug
17
serves to electrically connect the first doped region
12
a
to a storage node contact
40
to be discussed later. A second insulation film
19
operated as an interlayer insulation film is formed over the semiconductor substrate
1
.
As depicted in
FIG. 1
d
, the second insulation film
19
and the first insulation film
13
are sequentially patterned in accordance with the photoetching process using a photoresist film (not shown), and thus a second contact hole
21
is formed so that the upper surface of the second doped region
12
b
can be exposed.
As illustrated in
FIG. 1
e
, a second conductive film consisting of a polycrystalline silicon is formed in the second contact hole
21
and on the second insulation film
19
, and patterned by using a photoresist film (not shown), thereby forming the bit line
23
. The bit line
23
is electrically connected to the second doped region
12
b
. Then, a third insulation film
25
operated as an interlayer insulation film is formed over the semiconductor substrate
1
. After the third insulation film
25
is formed, a planarization process is performed.
As shown in
FIG. 1
f
, a first mask film consisting of a silicon or nitride is formed on the third insulation film
25
. The first mask film is patterned by using a photoresist film (not shown) as a mask, thereby forming a first mask film pattern
27
. Thereafter, a second mask film consisting of an identical material to the first mask film is formed over the semiconductor substrate
1
including the first mask film pattern
27
. An anisotropic etching process is performed on the second mask film without a mask, thereby forming second sidewall spacers
29
at both side portions of the first mask film pattern
27
. Hereinafter, a mask pattern consisting of the first mask film pattern
27
and the second sidewall spacers
29
are referred to as a ‘hard mask’.
Referring to
FIG. 1
g
, the third insulation film
25
and the second insulation film
19
are sequentially patterned by using the hard mask
31
as a mask, and thus a storage node contact hole
38
is formed so that the upper surface of the storage node contact plug
17
can be exposed.
As an integration degree of the semiconductor device is increased, a distance between the bit line
23
and the storage node contact plug
17
is reduced. Accordingly, if a misalignment is happened, the side portions of the bit line
23
may be exposed during the process of forming the storage node contact hole
38
. In this case, the storage node contact to be formed in the storage node contact hole and the bit line may be electrically short. It is thus required to prepare for the misalignment by decreasing a diameter of the storage node contact hole
38
. However, there is a limit to decrease the diameter of the storage node contact hole
38
in accordance with the photoetching process using a photoresist film. Therefore, the diameter of the storage node contact hole
38
is reduced as much as a width of the second sidewall spacer
29
by employing the hard mask
31
.
Referring to
FIG. 1
h
, a third conductive film consisting of a polycrystalline silicon is formed over the semiconductor substrate
1
including the storage node contact hole
38
. Then, an etching or CMP process is performed until the upper surface of the hard mask
31
is exposed, thereby forming the storage node contact
40
.
The storage node contact
40
serves to electrically connect a lower electrode
50
b
of the capacitor to the storage node contact plug
17
, and prevent the third insulation film
25
from being etched during a process of photoetching a fourth insulation film consisting of an oxide in order to form a fourth insulation film pattern
29
to be discussed later.
As depicted in
FIG. 1
i
, the fourth insulation film consisting of an oxide is formed on the hard mask
31
and the storage node contact
40
. The fourth insulation film is photoetched by using a photoresist film (not shown), and thus the fourth insulation film pattern
29
is formed so that the upper surface of the storage node contact
40
can be exposed. Thereafter, a fourth conductive film
50
forming the lower electrode of the capacitor is formed over the semiconductor substrate
1
including the fourth insulation film pattern
29
. The fourth conductive film
50
consists of a polycrystalline silicon. A fifth insulation film
33
consisting of an oxide is formed on the fourth conductive film
50
.
As illustrated in
FIG. 1
j
, an etching or CMP process is carried out until the upper surface of the fourth insulation film pattern
29
is exposed. Here, the lower electrode
50
b
is divided into storage cell units by the fourth insulation film pattern
29
.
As shown in
FIG. 1
k
, the fourth insulation film pattern
29
and the fifth insulation film
33
which consist of an oxide are removed according to a wet etching process. Here, the hard mask
31
consisting of a silicon or nitride prevents the third insulation film
25
from being etched. Then, a sixth insulation film
35
operated as a capacitor dielectric film is formed over the upper surface of the semiconductor substrate
1
including the lower electrode
50
b
. A fifth conductive film
37
consisting of a polycrystalline silicon and forming an upper electrode of the capacitor is formed on the sixth insulation film
35
. The fabrication of the conventional DRAM cell is thus finished.
According to the conventional method for fabricating the bit line and the capacitor of the DRAM cell as described above, the bit line
23
is formed, and then the third insulation film
25
operated as an interlayer insulation film is formed, as shown in
FIG. 1
e
.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Kennedy Jennifer M.
Niebling John F.
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